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Current sense amplifiers are used in a variety of applications, such as motor or solenoid control, load current monitoring, and fault detection. In such applications, it is typical for the input common-mode voltage to swing from ground to a certain high-side supply. While a user may assume that the input common-mode swings are limited to this high-side supply, transient voltages must be considered. The result of these transients is that a supposed low-voltage application tends to appear as a high-voltage application, and the current sense amplifier must be robust enough to handle these occurrences. This 2-page Application Note explains how to choose a suitable amplifier.
Heterodyne radios, such as the ADF7024 transceiver, use a mixer to downconvert received radio frequency (RF) signals to an intermediate frequency (IF). Interfering signals, called interferers, that lay on the image frequency are also mixed down to the wanted frequency. The interfering signals desensitize the receiver, resulting in blocking on the wanted channel. In theory, an ideal transceiver that employs an IQ receive architecture can be configured to prevent the image frequency from mixing onto the wanted channel. This assumes that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. This 6-page Application Note describes the fully autonomous image rejection (IR) calibration firmware download module for the ADF7024 transceiver IC.
This 8-page Application Note describes a reference design that improves the overall link budget by extending the range of the ADF7023 ISM band transceiver by almost 20 dB. In a non-interference-limited line-of-sight scenario, this equates to a range increase of approximately six to seven times. The design, which consists of an ADF7023 transceiver and an RFFM6901 front-end module, is suitable for operation in the 902 MHz to 928 MHz ISM band and complies with FCC regulations.
Current sense amplifiers are used to amplify small differential signals in the presence of large common-mode voltages, to measure the voltage across a shunt resistor, for example. Current sense amplifiers can operate with supply voltages as low as 1.8 V and withstand input common-mode voltages as high as 600 V. Many applications, including H-bridge motor drivers, solenoid controllers, and dc-to-dc switching converters, have common-mode voltages that vary as a function of time. An ideal current sense amplifier does not react to the input common-mode variation, but real current sense amplifiers have finite common-mode rejection, typically specified at about 100 μV/V (80 dB) at dc. This Application Note focuses on the common-mode step response of current sense amplifiers.
This 7-page Application Note describes the Reed-Solomon firmware module, which contains both forward error correction and advanced encryption standard (AES) encryption, for the ADF7023 transceiver. Reed-Solomon encoding appends check symbols to the transmitted data. When received, these symbols detect the presence of errors and correct them in the received data. The firmware module is flexible, allowing the user to select values that enable correction of up to five error bytes within a packet. Encoded packets are resilient to burst and random errors; their coding gain improves link margin.
This 11-page Application Note describes the radio performance of the ADF7021-N transceiver when configured for operation according to the wireless meter-bus (WM-Bus) standard, focusing on key receiver parameters applicable to the 2.4 kbps and 4.8 kbps modes of operation. These parameters are packet error rate (PER) over power, sensitivity over carrier frequency error, blocking, and adjacent channel selectivity.
Circuits from the Lab
This frequency selective, radio frequency (RF) detector offers a 90-dB detection range from 35 MHz to 4.4 GHz. Unlike a standalone detector that does not discriminate between signals in the frequency spectrum, this circuit can focus on a narrow band of frequencies, enhancing performance over the specified range. The rms responding circuit is stable vs. temperature and frequency, making it attractive for applications that require precise frequency control, selective RF power measurement, and strong immunity to unwanted blockers.
This true rms responding power detector uses a variable gain amplifier (VGA) and a power detector to provide a 95-dB wide detection range, making it useful for accurate measurement of signals with diverse or varying crest factors, such as those found in GSM/EDGE, CDMA, WCDMA, TD-SCDMA, and LTE receivers and transmitters. The 65-dB detection range of the ADL5902 rms detector is extended to 95 dB by the addition of the AD8368 linear-in-dB VGA.
This circuit provides two, 16-bit, fully isolated, universal analog input channels suitable for programmable logic controller (PLC) and distributed control system (DCS) modules. Both channels are software programmable and support a number of voltage and current ranges and thermocouple and RTD types. The inputs are protected for dc overvoltage conditions of ±30 V. The demonstration board contains two fully isolated universal input channels: in one, the voltage, current, thermocouple, and RTD inputs all share the same terminals to minimize the number of pins required; in the other, separate terminals for voltage/current inputs and thermocouple/RTD inputs provides a lower part count and component cost.
This flexible, frequency agile, direct conversion IF-to-baseband receiver features a fixed 5-dB conversion gain to reduce the cascaded noise figure. Variable baseband gain adjusts the signal level, and a programmable low-pass filter eliminates out-of-channel blockers and noise. The filter bandwidth can be dynamically adjusted as the input signal bandwidth changes, ensuring full use of the available dynamic range of the driven ADC. The core circuit is an integrated I/Q demodulator with fractional-N PLL and VCO. With a single variable reference frequency, the PLL/VCO can provide a local oscillator (LO) between 750 MHz and 1150 MHz.
Precision low-noise dual Operational Amplifier provides EMI and overvoltage protection
The ADA4177-2 dual op amp features 2-μV typ offset voltage, 1-μV/°C max drift, 1-nA max input bias current, and 8-nV/√Hz typ noise. The rail-to-rail outputs provide an 8% improvement in dynamic range and are stable with capacitive loads of more than 1000 pF with no external compensation; the inputs are protected against signal excursions 32 V beyond either supply and provide 70-dB rejection for electromagnetic interference (EMI) at 1000 MHz. Applications include sensor signal conditioning, process control front-ends, and precision diode power measurement in optical and wireless transmission systems. It is useful in line powered and portable instrumentation, precision filters, voltage or current measurement, and level setting. Operating on ±2.25-V to ±18-V supplies, the ADA4177-2 draws 500 µA per amplifier. Available in 8-lead SOIC and MSOP packages, it is specified from –40°C to +125°C and priced at $1.53 in 1000s.
Dual 105-MHz, low-noise, low-power, low-drift Operational Amplifier
The ADA4805-2 high-speed dual op amp offers rail-to-rail outputs, 125-μV maximum input offset voltage, 105-MHz unity-gain bandwidth, 160-V/μs slew rate, 5.9-nV/√Hz voltage noise, and 0.6-pA/√Hz current noise, making it ideal for low-power, high-resolution data-acquisition systems. Its 500-µA quiescent current per amplifier is reduced to 3 µA in shutdown mode; the output settles to 16 bits within 3 µs from shutdown to fully on, allowing the amplifier to be turned off between ADC samples. The ADA4805-2 operates on a single 2.7-V to 10-V supply or dual ±1.35-V to ±5-V supplies. Available in an 8-lead MSOP package, it is specified from –40°C to +125°C and priced at $1.64 in 1000s.
Single Comparator includes accurate reference voltage
The ADCMP394 low-power comparator with rail-to-rail inputs is ideal for use in battery powered applications. It features a common-mode input voltage range that extends 200 mV beyond the rails, 1-mV typical offset voltage across the full common-mode range, and a logic-low output when the supply voltage is less than the UVLO threshold. The 1-V ±0.9% buffered reference can connect directly to the comparator inputs, serving as the trip value for precision monitoring and detection of positive voltages; or as an offset when monitoring negative voltages. Operating on a 2.3-V to 5.5-V supply, the ADCMP394 draws 34 µA. Available in an 8-lead SOIC package, it is specified from –40°C to +125°C and priced at $0.37 in 1000s.
Ethernet/Gigabit Ethernet Clock Generator
The AD9574 multiple output clock generator comprises a dedicated phase-locked loop (PLL) core optimized for Ethernet and gigabit Ethernet line card applications. The high-performance, low-jitter integer-N PLL frequency synthesizer maximizes network performance. Configuration for a particular application is accomplished by connecting external pull-up or pull-down resistors to the program reader pins to establish frequency translations, clock output functionality, and input reference functionality. Connecting an external oscillator to one or both of the reference inputs results in a set of output frequencies as determined by the configuration. A stable clock source connected to the monitor clock input enables reference quality of service (QoS) status monitoring. The PLL consists of a low-noise phase-frequency detector (PFD), a precision charge pump (CP), a partially integrated loop filter (LF), a low phase noise voltage-controlled oscillator (VCO), and feedback and output dividers. The integrated loop filter requires only one external capacitor connected to the LF pin. Operating on a 2.97-V to 3.63-V supply, the AD9574 dissipates 698 mW with all blocks running, 569 mW in a typical configuration, and 422 mW in a minimal power configuration. Available in a 48-lead LFCSP package, it is specified from –40°C to +85°C and priced at $5.10 in 1000s.
Synchronous Demodulator and Configurable Analog Filter
The ADA2200 synchronous demodulator and configurable analog filter performs precision magnitude and phase measurements in low power sensor signal conditioning and data acquisition applications. Using sampled analog technology (SAT), the analog input, sampled analog output, device includes a low-pass 1/8× decimation finite impulse response (FIR) filter, a configurable infinite impulse response (IIR) filter, a mixer with 0°/90° phase selection, a reference clock, and an ADC driver output. All signal processing is performed in the analog domain, eliminating the effects of quantization noise and rounding errors, reducing downstream ADC sample rates, and offloading tasks from the digital processor. When the demodulation function is disabled, the device acts as a precision filter with programmable bandwidth and tunable center frequency. Single-ended and differential signal interfaces are possible on both input and output terminals, simplifying connection to other components. The low power consumption and rail-to-rail operation are ideal for battery-powered and low-voltage systems. On-chip clock generation produces a mixing signal with programmable frequency and phase. In addition, output signal synchronization eases interfacing to converters, multiplexers, and other sampled systems. Operating on a 2.7-V to 3.6-V supply, the ADA2200 draws 395 µA. Available in a 16-lead TSSOP package, it is specified from –40°C to +85°C and priced at $2.95 in 1000s.
Wideband Quadrature Modulator includes fractional-N PLL and four VCOs
The ADRF6720-27 wideband quadrature modulator with integrated synthesizer is ideally suited for 3G and 4G communication systems. Comprising a high-linearity broadband modulator, fractional-N phase-locked loop, and four low-phase-noise multicore VCOs, it offers digital programmability for carrier feedthrough optimization, sideband suppression, HD3/IP3 optimization, and high-side or low-side LO injection. The local oscillator (LO) can be generated externally, or internally via the on-chip integer-N and fractional-N-synthesizers. The multicore VCOs enable LO coverage from 356.25 MHz to 2855 MHz. Quadrature signals are generated with a divide-by-2 phase splitter or with a polyphase filter. Operating on a 3.3 V supply, the ADRF6720-27 draws 425 mA with the modulator enabled, 218 mA with the modulator disabled, and 14.5 mA in power-down mode. Available in a 40-lead LFCSP package, it is specified from –40°C to +85°C and priced at $7.95 in 1000s.
30-V, low-noise, low-power, Operational Amplifier provides rail-to-rail inputs/outputs
ADA4084-1 op amp features rail-to-rail inputs and
outputs. It specifies 100-µV max offset at room temperature,
105-MHz, low-noise, low-power, low-drift Operational Amplifier
ADA4805-1 high-speed op amp offers a rail-to-rail
output, 125-μV maximum input offset voltage, 105-MHz unity-gain bandwidth,
Single and dual Comparators have known power-up state
The single ADCMP391 and dual ADCMP392 low-power comparators with rail-to-rail inputs feature a common-mode input voltage range that extends 200 mV beyond the rails, 1-mV offset voltage across the full common-mode range, and an undervoltage lockout (UVLO) monitor, making them ideal for general-purpose and battery powered applications. The outputs have a defined state upon power-up, remaining at logic low until the supply voltage exceeds the UVLO threshold. Operating on a 2.3-V to 5.5-V supply, the ADCMP391/392 draw 19/22 µA. Available in 8-lead SOIC packages, they are specified from –40°C to +125°C and priced at $0.25/$0.34 in 1000s.
4-input, 4-output, Adaptive Clock Translator for multiservice line cards
The AD9554-1 low-loop-bandwidth clock translator provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). It generates an output clock synchronized to up to four external input references. The digital PLL (DPLL) reduces input time jitter and phase noise associated with the external references. The digitally controlled loop and holdover circuitry continues to generate a low-jitter output clock even when all reference inputs have failed. Four differential clock outputs at frequencies from 430 kHz to 941 MHz are individually configurable for HCSL-, LVDS-, or LVPECL compatibility. The devices support GR-1244 Stratum 3 stability in holdover mode, Telcordia GR‑253 jitter specifications in up to OC-192 systems, and ITU-T G.8262 synchronous Ethernet slave clocks. Operating on 1.8-V and 3.3-V supplies, the AD9554-1 dissipates 920 mW in typical configurations and 164 mW in power-down mode. Available in a 56-lead LFCSP packages, it is specified from –40°C to +85°C and priced at $20.81 in 1000s.
Dual digitally controlled RF VGA operates from 100 MHz to 4000 MHz
ADRF6573 dual high-performance, digitally
controlled, variable-gain amplifier (VGA) operates from 100 MHz to 4000 MHz.
Each channel includes a 6-bit digital step attenuator (DSA) with a 31.5-dB
gain control range, 0.5-dB steps, and
Ryan Curran, Qui Luu, and Maithil Pachchigar, RF-to-Bits Solution Offers Precise Phase and Magnitude Data for Material Analysis, Analog Dialogue, 2014-10-01
David Hunter, Two New Devices Help Reinvent the Signal Generator, Analog Dialogue, 2014-10-01
Bob Clarke and Kevin Kreitzer, Maximising the dynamic range of software defined radio, Electronic Product Design & Test, 2014-10-01
Duncan Bosworth, Software defined radio in the battlefield: Multiband analogue front end brings one chip radio closer to reality, New Electronics, 2014-09-09
Luis Orozco, How to… Make Precision Light Measurements with Large Area Photodiodes, Anglia Live, 2014-07-28
Gustavo Castro, The Diamond Plot, Analog Dialogue, 2014-07-02
Gustavo Castro, The Diamond Plot, Planet Analog, 2014-06-30
Vicky Wong, Zero-crossover-distortion amplifiers improve linearity of DAC Systems, Power Systems Design, 2014-06-01
Mark Reisiger, Creative Compensation Enables Tiny Amplifier to Drive 200-mW Loads, Analog Dialogue, 2014-05-05
James Bryant, Discretion is the better part… , Analog Dialogue, 2014-05-05
Qui Luu and Benjamin Sam, Differential Drive Optimizes Active Mixers, Microwaves&RF, 2014-04-11
James Bryant, Choosing Transistors, EDN, 2014-04-22
James Bryant, Current-Output Circuit Techniques Add Versatility to Your Analog Toolbox, Analog Dialogue, 2014-04-02
Chau Tran and Fotjana Bida, Difference Amplifiers Enable Low Loss, High-Performance Full-Wave Rectifier, Planet Analog, 2014-03-06
Harry Holt, A Deeper Look into Difference Amplifiers, Analog Dialogue, 2014-02-03
Rob Reeder, Designing for Wideband RF, EDN, 2014-01-28
Gustavo Castro and Scott Hunt, How to Stay Out of Deep Water when Designing with Bridge Sensors, Analog Dialogue, 2014-01-06
Kyle Slightom, Dual-Loop Clock Generator Cleans Jitter, Provides Multiple High-Frequency Outputs, Analog Dialogue, 2014-01-06
Sandro Herrera, Differential I/O low-power instrumentation amp, EDN, 2013-12-16
Developing Multiple-Input Multiple-Output (MIMO) Systems with the AD9361 - As software defined radio (SDR) and multiple-input multiple-output (MIMO) become more prevalent, there is a need for more channel diversity. This webcast will detail how to use multiple AD9361 RF agile transceivers to create an N×N MIMO system, as well as explore the available tradeoffs in the design. The AD9361 is a fully integrated 2×2 MIMO transceiver. Its programmability and wideband capability make it ideal for a broad range of transceiver applications.
The Spectrum of Current Sensing: From DC to Light - Current measurement is an essential part of sensor interface, control, power management, and communications. The span of current sensing is from picoamperes to kiloamperes, and from dc to gigahertz (or light, when using photodiodes). We will cover high power and motor control, 4–20 mA industrial communications, energy monitoring, photodiodes, isolation, and developing precision current sources. We will also show on-line tools for circuit design.
Digital Filter Design for Integrated RF Transceivers - This webcast introduces how MATLAB from MathWorks can be used for complicated filter design in wireless SDR systems and components. We will create a model of the Analog Devices AD9361 and AD9364 RF transceivers, as integrated on the AD-FMCOMMS2-EBZ and AD-FMCOMMS4-EBZ SDR development platforms. We will use that model to design a filter for the internal FIR filters using the generated coefficients in an example system design.
Integrated Software-Defined Radio on Zynq®-7000 All Programmable SoC -- This course introduces wireless communication system design on the new Avnet Zynq®-7000 All Programmable SoC/AD9361 Software-Defined Radio Evaluation Kit featuring Analog Devices AD9361 single-chip RF agile transceiver. An IEEE 802.11 receiver example will demonstrate system-level simulation using MATLAB® and Simulink® modeling and code generation tools from MathWorks. Using the Xilinx Vivado® Design Suite, the system will be implemented for production showing the receiver detecting 802.11 beacon frames in a stand-alone system running UBUNTU desktop Linux on Xilinx Zynq AP SoC. Presentations will alternate with instructor-led demos to illustrate coding techniques within MathWorks and Xilinx development tools for high-speed digital signal processing.
Introduction to Analog RMS-to-DC Technology: Converters and Applications – This webinar provides users with a better understanding of the underlying theory of rms, and how rms-to-dc converters work.
The Fundamentals of Voltage References and Current Sensing - This webcast will discuss voltage references and how they are used in circuit design. It will also cover and compare reference designs, specifications, reference alternatives, and application ideas such as negative references, then present how currents are handled, measured, and generated in system design.
Precision basics: How not to be surprised by unexpected error sources - This webcast, co-sponsored by Avnet EM, presents error sources of a few fundamental front end signal conditioning blocks and provides hints for better practices that will save money and speed development time.
Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS) – This concludes our two-part series on frequency synthesis with an introduction to direct digital synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
Fundamentals of Frequency Synthesis, Part 1: Phase Locked Loops – The first of a two-part series on frequency synthesis, with an introduction to phase locked loops (PLLs). This webcast looks at the need for frequency generation; techniques from the past, present, and future; how to assess the performance of a frequency synthesizer; and real world applications. Particular attention will be focused on phase locked loops as frequency synthesizers.
Fundamentals of the RF Transmission and Reception of Digital Signals - Digital Modulation is an important topic for RF designers because most modern day transceivers transmit and receive digitally modulated data. In this webcast, part of ADI's continuing FUNDAMENTALS OF DESIGN series we will introduce you to the challenges—and solutions—for digital modulation. This webcast is a great way for beginners to get introduced to this vital communications standard or for veteran RF designers learn what's new in the field.
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