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This 8-page Application Note describes a reference design that improves the overall link budget by extending the range of the ADF7023 ISM band transceiver by almost 20 dB. In a non-interference-limited line-of-sight scenario, this equates to a range increase of approximately six to seven times. The design, which consists of an ADF7023 transceiver and an RFFM6901 front-end module, is suitable for operation in the 902 MHz to 928 MHz ISM band and complies with FCC regulations.
This 7-page Application Note describes the Reed-Solomon firmware module, which contains both forward error correction and advanced encryption standard (AES) encryption, for the ADF7023 transceiver. Reed-Solomon encoding appends check symbols to the transmitted data. When received, these symbols detect the presence of errors and correct them in the received data. The firmware module is flexible, allowing the user to select values that enable correction of up to five error bytes within a packet. Encoded packets are resilient to burst and random errors; their coding gain improves link margin.
This 11-page Application Note describes the radio performance of the ADF7021-N transceiver when configured for operation according to the wireless meter-bus (WM-Bus) standard, focusing on key receiver parameters applicable to the 2.4 kbps and 4.8 kbps modes of operation. These parameters are packet error rate (PER) over power, sensitivity over carrier frequency error, blocking, and adjacent channel selectivity.
Heterodyne radios, such as the ADF7023 family of transceivers, use a mixer to downconvert received radio frequency (RF) signals to an intermediate frequency (IF). Interfering signals, called interferers, that lay on the image frequency are also mixed down to the wanted frequency. This desensitizes the receiver, resulting in blocking on the wanted channel. In theory, an ideal transceiver, which employs an IQ receive architecture, can be configured to eliminate the image frequency mixing onto the wanted channel. This theory assumes that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a firmware download module, until the quadrature signals are optimally balanced, providing maximum image rejection. This 6-page Application Note describes the fully autonomous image rejection (IR) calibration firmware download module for the ADF7023 transceiver IC. With minimum user input, this firmware optimizes the image rejection with a default configuration completely autonomously.
This 4-page Application Note provides information on the built-in packet error rate (PER) test mode on the ADF7023 and ADF7023-J. This mode helps the user to set up a communication link and test its quality. Up to 65,535 packets can be transmitted with a programmable delay between packets. The packet stored in packet RAM is transmitted each time. If the cyclic redundancy check (CRC) is correct, the receiver determines it has correctly received a packet.
When the ADF7023 receives a packet in packet mode, it stores the data in a linear sequence in the packet RAM. Prior to transmission, the data to be transmitted is written to the packet RAM in a linear sequence, as described in the ADF7023 data sheet. The ADF7023 packet RAM is 240 bytes long. If the packet length is greater than 240 bytes, additional measures are required. This 4-page Application Note describes a method for handling longer packet lengths on the ADF7023, up to a maximum length of 65,535 bytes, via a rolling buffer mechanism. This method reuses and renames several registers of the ADF7023.
This 11-page Application Note describes a reference design using the ADF7241/ADF7242 highly integrated, low power, high performance transceiver and the SE2431L fully integrated RF front-end. The ADF7241 and ADF7242, which operate in the global 2.4-GHz ISM band, provides flexibility, robustness, ease of use, and low current consumption. They support the IEEE 802.15.4-2006 2.4‑GHz PHY requirements. The ADF7242 also supports proprietary GFSK/FSK/GMSK/MSK modulation schemes in both packet and data streaming modes. The Skyworks SE2431L, designed for 2.4 GHz applications, provides ease of use and maximum flexibility, with fully matched 50 Ω input and output, integrated interstage matching, harmonic filter, and digital controls that are compatible with 1.6 V to 3.6 V CMOS levels.
Heterodyne radios, such as the ADF7021 family of transceivers, use a mixer to down convert received RF signals to an intermediate frequency (IF). The output of the mixer contains the wanted frequency component along with an unwanted component at the image frequency. Unwanted signals present at the image frequency can degrade receiver sensitivity, resulting in loss of signal on the wanted channel. In theory, transceivers employing an I/Q receive architecture can be configured to infinitely reject the image frequency, assuming that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a digital control register until the quadrature signals are optimally balanced, providing maximum image rejection. This 11-page Application Note provides information on the mechanism that generates the image frequency and describes how image calibration can be implemented on the ADF7021, ADF7021-N, and ADF7021-V.
Circuits from the Lab
This true rms responding power detector uses a variable gain amplifier (VGA) and a power detector to provide a 95-dB wide detection range, making it useful for accurate measurement of signals with diverse or varying crest factors, such as those found in GSM/EDGE, CDMA, WCDMA, TD-SCDMA, and LTE receivers and transmitters. The 65-dB detection range of the ADL5902 rms detector is extended to 95 dB by the addition of the AD8368 linear-in-dB VGA.
This circuit provides two, 16-bit, fully isolated, universal analog input channels suitable for programmable logic controller (PLC) and distributed control system (DCS) modules. Both channels are software programmable and support a number of voltage and current ranges and thermocouple and RTD types. The inputs are protected for dc overvoltage conditions of ±30 V. The demonstration board contains two fully isolated universal input channels: in one, the voltage, current, thermocouple, and RTD inputs all share the same terminals to minimize the number of pins required; in the other, separate terminals for voltage/current inputs and thermocouple/RTD inputs provides a lower part count and component cost.
This flexible, frequency agile, direct conversion IF-to-baseband receiver features a fixed 5-dB conversion gain to reduce the cascaded noise figure. Variable baseband gain adjusts the signal level, and a programmable low-pass filter eliminates out-of-channel blockers and noise. The filter bandwidth can be dynamically adjusted as the input signal bandwidth changes, ensuring full use of the available dynamic range of the driven ADC. The core circuit is an integrated I/Q demodulator with fractional-N PLL and VCO. With a single variable reference frequency, the PLL/VCO can provide a local oscillator (LO) between 750 MHz and 1150 MHz.
This configurable 4 mA-to-20 mA loop-powered transmitter is based on an industry-leading micropower instrumentation amplifier. Total unadjusted error is less than 1%. It can be configured with a single switch as either a transmitter that converts a differential input voltage into a current output, or as a receiver that converts a 4 mA-to-20 mA current input to a voltage output. Optimized for precision, low noise and low power industrial process control applications, the circuit can accept 0 V to 5V or 0 V to 10 V input range as a transmitter. As a receiver it can provide 0.2 V to 2.3 V or 0.2 V to 4.8 V output range compatible with ADCs using 2.5 V or 5 V references. The supply voltage can range from 12 V to 36 V as a transmitter and 7 V to 36 V as a receiver. The circuit is configurable, so a single hardware design can be used as a backup for both transmitter and receiver at the same time, minimizing inventory requirements.
This dual-channel colorimeter, which features a modulated light source transmitter and a synchronous detector receiver, measures the ratio of light absorbed by the sample and reference containers at three different wavelengths, providing an efficient solution for many chemical analysis and environmental monitoring instruments that measure concentrations and characterize materials through absorption spectroscopy.
Quad JFET-input Op Amp features low noise, high precision, low bias current, rail-to-rail outputs
The ADA4610-4 quad precision JFET-input amplifier features 1-mV max offset, 8-µV/°C max offset drift, 5-pA bias current, 110-dB common-mode rejection, 98-dB open-loop gain, 7.3-nV/rt-Hz noise, 9.5-MHz bandwidth, 25-V/µs slew rate, and rail-to-rail outputs, making it well-suited for precise, low-level measurements in sensor front-ends, medical instruments, and automated test equipment. Fast settling is maintained with substantial capacitive loads, and the output avoids phase reversal when input voltages exceed the maximum common-mode voltage range. Operating on ±4.5-V to ±18-V supplies, the ADA4610-4 draws 1.5 mA per amplifier. Available in a 14-lead SOIC package, it is specified from –40°C to +125°C and priced at $3.65 in 1000s.
High-speed, high-voltage Op Amp provides 1-A output drive
The ADA4870 unity gain stable, high-speed, current-feedback amplifier can deliver 1-A output current and 2500-V/μs slew rate from a 40-V supply. Its innovative architecture enables high output power, high-speed signal processing in applications that use a low-impedance load, making it ideal for driving high-voltage power FETs, piezo transducers, PIN diodes, and CCD panels. Operating on ±5-V to ±20-V supplies, the ADA4870 draws 32.5 mA in normal mode and 0.75 mA in shutdown mode. Available in a 20-lead power SOIC package, it is specified from –40°C to +85°C and priced at $8.50 in 1000s.
The ADCMP393 low-power quad comparator with rail-to-rail inputs is ideal for use in battery powered applications. It features a common-mode input voltage range that extends 200 mV beyond the rails, an offset voltage of 1 mV typical across the full common-mode range, and a logic-low output when the supply voltage is less than the UVLO threshold. Operating on a 2.3-V to 5.5-V supply, the ADCMP393 draws 26.8 µA. Available in a 14-lead SOIC package, it is specified from –40°C to +125°C and priced at $0.49 in 1000s.
Analog Front-End for radar receive path includes ADC, 4-channel LNA/PGA/AAF
The AD8285 analog front-end for radar receive paths includes four channels of low-noise amplifier (LNA), programmable-gain amplifier (PGA), and antialiasing filter (AAF), plus a direct-to-ADC channel, a 5-channel multiplexer, and a 12-bit ADC. Each channel has a 16-dB to 34-dB gain range in 6-dB increments; and the ADC converts at up to 72 MSPS. The combined input referred noise voltage of the entire channel is 3.5 nV/√Hz at maximum gain. Designed for low cost, low power, compact size, flexibility, and ease of use, the device is optimized for dynamic performance and low power in applications where a small package size is critical. Operating on 1.8-V and 3.3-V supplies, the AD8285 dissipates 185 mW in normal mode and 5 mW in power-down mode. Available in a 72-lead power LFCSP package, it is specified from –40°C to +105°C and priced at $8.33 in 1000s.
Quad Comparator includes accurate reference voltage
The ADCMP396 low-power quad comparator with rail-to-rail inputs is ideal for use in battery powered applications. It features a common-mode input voltage range that extends 200 mV beyond the rails, an offset voltage of 1 mV typical across the full common-mode range, and a logic-low output when the supply voltage is less than the UVLO threshold. The 1-V buffered reference can connect directly to the comparator inputs, serving as the trip value for precision monitoring and detection of positive voltages; or as an offset when monitoring negative voltages. Operating on a 2.3-V to 5.5-V supply, the ADCMP396 draws 42 µA. Available in a 16-lead SOIC package, it is specified from –40°C to +125°C and priced at $0.98 in 1000s.
Integer-N/Fractional-N PLL Synthesizer
The ADF4155 implements fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter, VCO, and reference frequency up to 8 GHz. The high-resolution programmable modulus allows synthesis of exact frequencies. The VCO frequency can be divided by 1, 2, 4, 8, 16, 32, or 64 to generate RF output frequencies as low as 7.8125 MHz. All on-chip registers are controlled via a simple 3-wire interface. Operating on a 3.3-V supply, the ADF4155 draws 105 mA with the RF output enabled, 38 mA with the RF output disabled, 500 µA in software power-down mode, and 10 µA in hardware power-down mode. Available in a 24-lead LFCSP package, it is specified from –40°C to +85°C and priced at $5.02 in 1000s.
3-GHz Variable-Gain LNA includes 500-mW driver amplifier
The ADL5246 high-performance, low-noise variable-gain amplifier (VGA) is optimized for multistandard base station receivers and point-to-point receive (Rx) and transmit (Tx) applications. It consists of a low-noise amplifier, a high-linearity VGA, and a 500-mW output stage. The variable attenuator networks are optimized to provide high linearity over the 45-dB gain-control range. Gain is set using a 0-V to 3.3-V control voltage. The output stage is an externally tuned 500-mW driver amplifier that can be optimized anywhere in the 0.6-GHz to 3-GHz range, with a 200-MHz average tuning bandwidth. An external filter can be used between the VGA and the driver amplifier. The ADL5246 can be biased between 3.3 V and 5 V to trade-off between performance and power consumption, drawing 270 mA at 5 V and 141 mA at 3.3 V. Available in a 32-lead LFCSP package, it is specified from –40°C to +105°C and priced at $7.50 in 1000s.
Continuous-rate 8.5-Mbps to 11.3-Gbps Clock and Data Recovery IC with integrated limiting amp and equalizer
The ADN2917 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 8.5 Mbps to 11.3 Gbps, automatically locking to all data rates without an external reference clock. Its jitter performance exceeds all SONET/SDH requirements, including jitter transfer, jitter generation, and jitter tolerance. It provides manual or automatic slice adjust and manual sample phase adjusts; and users can select a limiting amplifier, adaptive or manually adjustable equalizer, or bypass at the input. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a programmable threshold. Hysteresis prevents chatter at the LOS output. The input signal strength can be read through the I2C registers. The device supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. Operating on 1.2-V, 1.8-V, and 3.3-V supplies, the ADN2917 dissipates 446.6 mW at 8.5 Gbps. Available in a 24-lead LFCSP package, it is specified from –40°C to +85°C and priced at $19.95 in 1000s.
Wideband Quadrature Modulator includes fractional-N PLL and four VCOs
The ADRF6720 wideband quadrature modulator with integrated synthesizer is ideally suited for 3G and 4G communication systems. Comprising a high-linearity broadband modulator, fractional-N phase-locked loop, and four low-phase-noise multicore VCOs, it offers digital programmability for carrier feedthrough optimization, sideband suppression, HD3/IP3 optimization, and high-side or low-side LO injection. The local oscillator (LO) can be generated externally, or internally via the on-chip integer-N and fractional-N-synthesizers. The multicore VCOs enable LO coverage from 356.25 MHz to 2855 MHz. Quadrature signals are generated with a divide-by-2 phase splitter or with a polyphase filter. Operating on a 3.3 V supply, the ADRF6720 draws 425 mA with the modulator enabled, 228 mA with the modulator disabled, and 14.5 mA in power-down mode. Available in a 40-lead LFCSP package, it is specified from –40°C to +85°C and priced at $7.95 in 1000s.
4-input, 8-output, Adaptive Clock Translator for multiservice line cards
AD9554 low-loop-bandwidth clock translator
provides jitter cleanup and synchronization for many systems, including
synchronous optical networks (SONET/SDH). It generates an output clock
synchronized to up to four external input references. The digital PLL (DPLL)
reduces input time jitter and phase noise associated with the external
references. The digitally controlled loop and holdover circuitry continues
to generate a low-jitter output clock even when all reference inputs have
failed. Eight differential clock outputs at frequencies from 430 kHz to 941
MHz are individually configurable for HCSL-, LVDS-, or LVPECL compatibility.
The devices support GR-1244 Stratum 3 stability in holdover mode, Telcordia
GR‑253 jitter specifications in up to OC-192 systems, and
Vicky Wong, Zero-crossover-distortion amplifiers improve linearity of DAC Systems, Power Systems Design, 2014-06-01
Mark Reisiger, Creative Compensation Enables Tiny Amplifier to Drive 200-mW Loads, Analog Dialogue, 2014-05-05
James Bryant, Discretion is the better part… , Analog Dialogue, 2014-05-05
Qui Luu and Benjamin Sam, Differential Drive Optimizes Active Mixers, Microwaves&RF, 2014-04-11
James Bryant, Choosing Transistors, EDN, 2014-04-22
James Bryant, Current-Output Circuit Techniques Add Versatility to Your Analog Toolbox, Analog Dialogue, 2014-04-02
Chau Tran and Fotjana Bida, Difference Amplifiers Enable Low Loss, High-Performance Full-Wave Rectifier, Planet Analog, 2014-03-06
Harry Holt, A Deeper Look into Difference Amplifiers, Analog Dialogue, 2014-02-03
Rob Reeder, Designing for Wideband RF, EDN, 2014-01-28
Gustavo Castro and Scott Hunt, How to Stay Out of Deep Water when Designing with Bridge Sensors, Analog Dialogue, 2014-01-06
Kyle Slightom, Dual-Loop Clock Generator Cleans Jitter, Provides Multiple High-Frequency Outputs, Analog Dialogue, 2014-01-06
Sandro Herrera, Differential I/O low-power instrumentation amp, EDN, 2013-12-16
Rob Reeder, Analog Fundamentals: Amplifiers, EDN, 2013-10-06
Sandro Herrera, Measure Frequency Response on Fully Differential Amplifiers Using Complex Algebra, Design News, 2013-10-01
George Alexandrov and Nathan Carter, Some Tips on Making a FETching Discrete Amplifier, Analog Dialogue, 2013-10-01
Rob Reeder, Analog Fundamentals: High-Speed PCB Design, EDN, 2013-09-17
John Ardizzoni, Efficiently Design An Op-Amp Summer Circuit, Electronic Design, 2013-08-26
Charly El-Khoury, Amplifier Disable Function Eliminates Need for Multiplexers in Multichannel Applications, Analog Dialogue, 2013-08-04
John Ardizzoni, How to Choose an Op Amp, CQ, 2013-08-01
Jonathan Pearson, Compensating Current Feedback Amplifiers in Photocurrent Applications, Analog Dialogue, 2013-07-02
Alan Walsh, Voltage Reference Design for Precision Successive-Approximation ADCs, Analog Dialogue, 2013-06-03
James Bryant, Multipliers vs. Modulators, Analog Dialogue, 2013-06-03
John Ardizzoni, Crystal Radio Sets and Op Amps, Analog Dialogue, 2013-06-03
Developing Multiple-Input Multiple-Output (MIMO) Systems with the AD9361 - As software defined radio (SDR) and multiple-input multiple-output (MIMO) become more prevalent, there is a need for more channel diversity. This webcast will detail how to use multiple AD9361 RF agile transceivers to create an N×N MIMO system, as well as explore the available tradeoffs in the design. The AD9361 is a fully integrated 2×2 MIMO transceiver. Its programmability and wideband capability make it ideal for a broad range of transceiver applications.
The Spectrum of Current Sensing: From DC to Light - Current measurement is an essential part of sensor interface, control, power management, and communications. The span of current sensing is from picoamperes to kiloamperes, and from dc to gigahertz (or light, when using photodiodes). We will cover high power and motor control, 4–20 mA industrial communications, energy monitoring, photodiodes, isolation, and developing precision current sources. We will also show on-line tools for circuit design.
Digital Filter Design for Integrated RF Transceivers - This webcast introduces how MATLAB from MathWorks can be used for complicated filter design in wireless SDR systems and components. We will create a model of the Analog Devices AD9361 and AD9364 RF transceivers, as integrated on the AD-FMCOMMS2-EBZ and AD-FMCOMMS4-EBZ SDR development platforms. We will use that model to design a filter for the internal FIR filters using the generated coefficients in an example system design.
Integrated Software-Defined Radio on Zynq®-7000 All Programmable SoC -- This course introduces wireless communication system design on the new Avnet Zynq®-7000 All Programmable SoC/AD9361 Software-Defined Radio Evaluation Kit featuring Analog Devices AD9361 single-chip RF agile transceiver. An IEEE 802.11 receiver example will demonstrate system-level simulation using MATLAB® and Simulink® modeling and code generation tools from MathWorks. Using the Xilinx Vivado® Design Suite, the system will be implemented for production showing the receiver detecting 802.11 beacon frames in a stand-alone system running UBUNTU desktop Linux on Xilinx Zynq AP SoC. Presentations will alternate with instructor-led demos to illustrate coding techniques within MathWorks and Xilinx development tools for high-speed digital signal processing.
Introduction to Analog RMS-to-DC Technology: Converters and Applications – This webinar provides users with a better understanding of the underlying theory of rms, and how rms-to-dc converters work.
The Fundamentals of Voltage References and Current Sensing - This webcast will discuss voltage references and how they are used in circuit design. It will also cover and compare reference designs, specifications, reference alternatives, and application ideas such as negative references, then present how currents are handled, measured, and generated in system design.
Precision basics: How not to be surprised by unexpected error sources - This webcast, co-sponsored by Avnet EM, presents error sources of a few fundamental front end signal conditioning blocks and provides hints for better practices that will save money and speed development time.
Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS) – This concludes our two-part series on frequency synthesis with an introduction to direct digital synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
Fundamentals of Frequency Synthesis, Part 1: Phase Locked Loops – The first of a two-part series on frequency synthesis, with an introduction to phase locked loops (PLLs). This webcast looks at the need for frequency generation; techniques from the past, present, and future; how to assess the performance of a frequency synthesizer; and real world applications. Particular attention will be focused on phase locked loops as frequency synthesizers.
Fundamentals of the RF Transmission and Reception of Digital Signals - Digital Modulation is an important topic for RF designers because most modern day transceivers transmit and receive digitally modulated data. In this webcast, part of ADI's continuing FUNDAMENTALS OF DESIGN series we will introduce you to the challenges—and solutions—for digital modulation. This webcast is a great way for beginners to get introduced to this vital communications standard or for veteran RF designers learn what's new in the field.
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