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This 7-page Application Note describes the Reed-Solomon firmware module, which contains both forward error correction and advanced encryption standard (AES) encryption, for the ADF7023 transceiver. Reed-Solomon encoding appends check symbols to the transmitted data. When received, these symbols detect the presence of errors and correct them in the received data. The firmware module is flexible, allowing the user to select values that enable correction of up to five error bytes within a packet. Encoded packets are resilient to burst and random errors; their coding gain improves link margin.
This 11-page Application Note describes the radio performance of the ADF7021-N transceiver when configured for operation according to the wireless meter-bus (WM-Bus) standard, focusing on key receiver parameters applicable to the 2.4 kbps and 4.8 kbps modes of operation. These parameters are packet error rate (PER) over power, sensitivity over carrier frequency error, blocking, and adjacent channel selectivity.
Heterodyne radios, such as the ADF7023 family of transceivers, use a mixer to downconvert received radio frequency (RF) signals to an intermediate frequency (IF). Interfering signals, called interferers, that lay on the image frequency are also mixed down to the wanted frequency. This desensitizes the receiver, resulting in blocking on the wanted channel. In theory, an ideal transceiver, which employs an IQ receive architecture, can be configured to eliminate the image frequency mixing onto the wanted channel. This theory assumes that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a firmware download module, until the quadrature signals are optimally balanced, providing maximum image rejection. This 6-page Application Note describes the fully autonomous image rejection (IR) calibration firmware download module for the ADF7023 transceiver IC. With minimum user input, this firmware optimizes the image rejection with a default configuration completely autonomously.
This 4-page Application Note provides information on the built-in packet error rate (PER) test mode on the ADF7023 and ADF7023-J. This mode helps the user to set up a communication link and test its quality. Up to 65,535 packets can be transmitted with a programmable delay between packets. The packet stored in packet RAM is transmitted each time. If the cyclic redundancy check (CRC) is correct, the receiver determines it has correctly received a packet.
When the ADF7023 receives a packet in packet mode, it stores the data in a linear sequence in the packet RAM. Prior to transmission, the data to be transmitted is written to the packet RAM in a linear sequence, as described in the ADF7023 data sheet. The ADF7023 packet RAM is 240 bytes long. If the packet length is greater than 240 bytes, additional measures are required. This 4-page Application Note describes a method for handling longer packet lengths on the ADF7023, up to a maximum length of 65,535 bytes, via a rolling buffer mechanism. This method reuses and renames several registers of the ADF7023.
This 11-page Application Note describes a reference design using the ADF7241/ADF7242 highly integrated, low power, high performance transceiver and the SE2431L fully integrated RF front-end. The ADF7241 and ADF7242, which operate in the global 2.4-GHz ISM band, provides flexibility, robustness, ease of use, and low current consumption. They support the IEEE 802.15.4-2006 2.4‑GHz PHY requirements. The ADF7242 also supports proprietary GFSK/FSK/GMSK/MSK modulation schemes in both packet and data streaming modes. The Skyworks SE2431L, designed for 2.4 GHz applications, provides ease of use and maximum flexibility, with fully matched 50 Ω input and output, integrated interstage matching, harmonic filter, and digital controls that are compatible with 1.6 V to 3.6 V CMOS levels.
Heterodyne radios, such as the ADF7021 family of transceivers, use a mixer to down convert received RF signals to an intermediate frequency (IF). The output of the mixer contains the wanted frequency component along with an unwanted component at the image frequency. Unwanted signals present at the image frequency can degrade receiver sensitivity, resulting in loss of signal on the wanted channel. In theory, transceivers employing an I/Q receive architecture can be configured to infinitely reject the image frequency, assuming that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a digital control register until the quadrature signals are optimally balanced, providing maximum image rejection. This 11-page Application Note provides information on the mechanism that generates the image frequency and describes how image calibration can be implemented on the ADF7021, ADF7021-N, and ADF7021-V.
This circuit provides a low cost, low power video multiplexer using the ADA4853-2 dual high speed amplifier, allowing a fourth video input to an ADV7180 3-channel video decoder, saving cost and board space.
Circuits from the Lab
This true rms responding power detector uses a variable gain amplifier (VGA) and a power detector to provide a 95-dB wide detection range, making it useful for accurate measurement of signals with diverse or varying crest factors, such as those found in GSM/EDGE, CDMA, WCDMA, TD-SCDMA, and LTE receivers and transmitters. The 65-dB detection range of the ADL5902 rms detector is extended to 95 dB by the addition of the AD8368 linear-in-dB VGA.
This circuit provides two, 16-bit, fully isolated, universal analog input channels suitable for programmable logic controller (PLC) and distributed control system (DCS) modules. Both channels are software programmable and support a number of voltage and current ranges and thermocouple and RTD types. The inputs are protected for dc overvoltage conditions of ±30 V. The demonstration board contains two fully isolated universal input channels: in one, the voltage, current, thermocouple, and RTD inputs all share the same terminals to minimize the number of pins required; in the other, separate terminals for voltage/current inputs and thermocouple/RTD inputs provides a lower part count and component cost.
This flexible, frequency agile, direct conversion IF-to-baseband receiver features a fixed 5-dB conversion gain to reduce the cascaded noise figure. Variable baseband gain adjusts the signal level, and a programmable low-pass filter eliminates out-of-channel blockers and noise. The filter bandwidth can be dynamically adjusted as the input signal bandwidth changes, ensuring full use of the available dynamic range of the driven ADC. The core circuit is an integrated I/Q demodulator with fractional-N PLL and VCO. With a single variable reference frequency, the PLL/VCO can provide a local oscillator (LO) between 750 MHz and 1150 MHz.
This dual-channel colorimeter, which features a modulated light source transmitter and a synchronous detector receiver, measures the ratio of light absorbed by the sample and reference containers at three different wavelengths, providing an efficient solution for many chemical analysis and environmental monitoring instruments that measure concentrations and characterize materials through absorption spectroscopy.
This broadband direct-conversion transmitter (analog baseband in, RF out) supports RF frequencies from 30 MHz to 2.2 GHz using a phase-locked loop (PLL) with an on-chip broadband voltage-controlled oscillator (VCO). Unlike modulators that use a divide-by-1 local oscillator (LO) stage, harmonic filtering of the LO is not required as long as the LO inputs to the modulator are driven differentially. The ADF4351 provides differential RF outputs and is, therefore, an excellent match. This PLL-to-modulator interface is useful for all I/Q modulators and I/Q demodulators that contain a 2XLO-based phase splitter.
This PLL circuit uses a 13-GHz fractional-N synthesizer, wideband active loop filter, and VCO, to achieve phase settling time of less than 5 μs to within 5° for a 200-MHz frequency jump. The performance is achieved using an active loop filter with 2.4-MHz bandwidth. This wideband loop filter is enabled by the 110-MHz maximum frequency of the ADF4159’s phase-frequency detector (PFD); and the 145-MHz gain-bandwidth product of the AD8065 op amp. The AD8065 can operate on a 24 V supply voltage, allowing control of most wideband VCOs having tuning voltages from 0 V to 18 V.
This complete adjustment-free linear variable differential transformer (LVDT) signal conditioning circuit can accurately measure linear displacement (position). The LVDT is a highly reliable sensor because the magnetic core can move without friction and does not touch the inside of the tube. Therefore, LVDTs are suitable for flight control feedback systems, position feedback in servomechanisms, automated measurement in machine tools, and many other industrial and scientific electromechanical applications where long term reliability is important. This circuit uses the AD698 LVDT signal conditioner, which contains a sine wave oscillator and a power amplifier to generate the excitation signals that drive the primary side of the LVDT. The AD698 also converts the secondary output into a dc voltage. The AD8615 rail-to-rail amplifier buffers the output of the AD698 and drives a low power 12-bit successive approximation analog-to-digital converter (ADC). The system has 82-dB dynamic range and 250-Hz system bandwidth, making it ideal for precision industrial position and gauging applications.
High-precision Op Amp features low offset, wide bandwidth, and low noise
ADA4077-1 operational amplifier features
25-/50-µV max offset and 0.25-/0.55-µV/°C max drift (B-/A-grades); 1-nA max
input bias current, 3.9-MHz bandwidth, 1.2-V/µs slew rate, 7‑nV/√Hz noise;
and outputs that are stable with capacitive loads to beyond 1000 pF with no
external compensation. This combination of specifications makes the
amplifier ideal for sensor signal conditioning, process control front ends,
portable instrumentation, and precision filters. Operating on a ±2.5-V to
±18‑V supply, the ADA4077-1 draws 400 μA. Specified from
695-MHz to 2700-MHz Quadrature Demodulator includes fractional-N PLL, VCO
The ADRF6820 highly integrated demodulator and synthesizer is ideally suited for next-generation communication systems. The feature rich device consists of a high-linearity broadband I/Q demodulator, a fractional-N phase-locked loop (PLL), a low phase noise multicore voltage-controlled oscillator (VCO, a 2:1 RF switch, a tunable RF balun, a programmable RF attenuator, and two low dropout (LDO) regulators. The high isolation 2:1 RF switch and tunable RF balun support two single-ended, 50-Ω terminated RF inputs. The programmable attenuator offers a 0-dB to 15-dB attenuation range with a 1‑dB step size to ensure an optimal differential RF input level. The differential local oscillator (LO) input signal can be generated externally via a high-frequency, low-phase-noise LO signal or internally via the fractional-N synthesizer, which enables continuous LO coverage from 356.25 MHz to 2850 MHz. The PLL reference input supports a wide frequency range; divide or multiply blocks can increase or decrease the reference frequency to the desired value before it is passed to the phase frequency detector (PFD). When selected, the output of the fractional-N synthesizer is applied to a divide-by-2 quadrature phase splitter. From the external LO path, a 1× LO signal can be applied to the built-in polyphase filter, or a 2× LO signal can be used with the divide-by-2 quadrature phase splitter to generate the quadrature LO inputs to the mixers. Operating on 3.3-V and 5-V supplies, the ADRF6820 dissipates 1.4 W with internal PLL and VCO and 1.1 W with an external filter. Available in a 40-lead LFCSP package, it is specified from –40°C to +85°C and priced at $12.98 in 1000s.
Quad, 30-V, low-noise, low-power, Operational Amplifier provides rail-to-rail inputs/outputs
ADA4084-4 quad operational amplifier features
rail-to-rail inputs and outputs. It specifies 100-µV max offset at room
Bidirectional zero-drift Current Sense Amplifiers
AD8417/AD8418A high-voltage current-sense
amplifiers measure bidirectional currents across a shunt resistor in a
variety of applications, including motor control, battery management, and
solenoid control. With buffered outputs that directly interface with most
ADCs, they feature 100-dB common-mode rejection from −2 V to +70 V, a gain
of 60/20 V/V, and ±0.3/0.2% max gain error over temperature. Their
zero-drift core achieves ±200 μV offset with 0.1-μV/°C offset drift over
temperature and common-mode range. Fully qualified for automotive
applications, the amplifiers include EMI filters and patented circuitry that
ensures output accuracy with pulse-width modulated common-mode voltages.
Operating with a 2.7-V to 5.5-V supply, the AD8417/18A draw 4.1 mA.
Specified from –40°C to +125°C, they are available in
Harry Holt, A Deeper Look into Difference Amplifiers, Analog Dialogue, 2014-02-03
Rob Reeder, Designing for Wideband RF, EDN, 2014-01-28
Gustavo Castro and Scott Hunt, How to Stay Out of Deep Water when Designing with Bridge Sensors, Analog Dialogue, 2014-01-06
Kyle Slightom, Dual-Loop Clock Generator Cleans Jitter, Provides Multiple High-Frequency Outputs, Analog Dialogue, 2014-01-06
Sandro Herrera, Differential I/O low-power instrumentation amp, EDN, 2013-12-16
Rob Reeder, Analog Fundamentals: Amplifiers, EDN, 2013-10-06
Sandro Herrera, Measure Frequency Response on Fully Differential Amplifiers Using Complex Algebra, Design News, 2013-10-01
George Alexandrov and Nathan Carter, Some Tips on Making a FETching Discrete Amplifier, Analog Dialogue, 2013-10-01
Rob Reeder, Analog Fundamentals: High-Speed PCB Design, EDN, 2013-09-17
John Ardizzoni, Efficiently Design An Op-Amp Summer Circuit, Electronic Design, 2013-08-26
Charly El-Khoury, Amplifier Disable Function Eliminates Need for Multiplexers in Multichannel Applications, Analog Dialogue, 2013-08-04
John Ardizzoni, How to Choose an Op Amp, CQ, 2013-08-01
Jonathan Pearson, Compensating Current Feedback Amplifiers in Photocurrent Applications, Analog Dialogue, 2013-07-02
Alan Walsh, Voltage Reference Design for Precision Successive-Approximation ADCs, Analog Dialogue, 2013-06-03
James Bryant, Multipliers vs. Modulators, Analog Dialogue, 2013-06-03
John Ardizzoni, Crystal Radio Sets and Op Amps, Analog Dialogue, 2013-06-03
Luis Orozco, Programmable-Gain Transimpedance Amplifiers Maximize Dynamic Range in Spectroscopy Systems, Analog Dialogue, 2013-05-01
David Buchanan, Input Magic, Analog Dialogue, 2013-05-01
Umesh Jayamohan, Understanding How Amplifier Noise Contributes to Total Noise in ADC Signal Chains, TechOnline India, 2013-04-30
David Guo, Choose Resistors to Minimize Errors in Grounded-Load Current Source, Analog Dialogue, 2013-04-01
James Bryant, Multipliers or Modulators, Analog Dialogue, 2013-04-01
John Ardizzoni, Noise Gain vs. Signal Gain, Analog Dialogue, 2013-03-06
Ryan Fletcher and Scott Wayne, Analog Devices' Engineering University--Why YOU Should Attend, Analog Dialogue, 2013-03-06
Ashraf Elghamrawi, High Performance Driver Amplifiers, Microwave Journal, 2013-02-14
Chau Tran, Marco Ablao, and Sherwin Gatchalian, Differential input to differential output amplifiers equal high temp solution, EE Times, 2013-02-06
Umesh Jayamohan, Understand How Amplifier Noise Contributes to Total Noise in ADC Signal Chains, Analog Dialogue, 2013-02-04
Digital Filter Design for Integrated RF Transceivers - This webcast introduces how MATLAB from MathWorks can be used for complicated filter design in wireless SDR systems and components. We will create a model of the Analog Devices AD9361 and AD9364 RF transceivers, as integrated on the AD-FMCOMMS2-EBZ and AD-FMCOMMS4-EBZ SDR development platforms. We will use that model to design a filter for the internal FIR filters using the generated coefficients in an example system design.
Integrated Software-Defined Radio on Zynq®-7000 All Programmable SoC -- This course introduces wireless communication system design on the new Avnet Zynq®-7000 All Programmable SoC/AD9361 Software-Defined Radio Evaluation Kit featuring Analog Devices AD9361 single-chip RF agile transceiver. An IEEE 802.11 receiver example will demonstrate system-level simulation using MATLAB® and Simulink® modeling and code generation tools from MathWorks. Using the Xilinx Vivado® Design Suite, the system will be implemented for production showing the receiver detecting 802.11 beacon frames in a stand-alone system running UBUNTU desktop Linux on Xilinx Zynq AP SoC. Presentations will alternate with instructor-led demos to illustrate coding techniques within MathWorks and Xilinx development tools for high-speed digital signal processing.
Introduction to Analog RMS-to-DC Technology: Converters and Applications – This webinar provides users with a better understanding of the underlying theory of rms, and how rms-to-dc converters work.
The Fundamentals of Voltage References and Current Sensing - This webcast will discuss voltage references and how they are used in circuit design. It will also cover and compare reference designs, specifications, reference alternatives, and application ideas such as negative references, then present how currents are handled, measured, and generated in system design.
Precision basics: How not to be surprised by unexpected error sources - This webcast, co-sponsored by Avnet EM, presents error sources of a few fundamental front end signal conditioning blocks and provides hints for better practices that will save money and speed development time.
Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS) – This concludes our two-part series on frequency synthesis with an introduction to direct digital synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
Fundamentals of Frequency Synthesis, Part 1: Phase Locked Loops – The first of a two-part series on frequency synthesis, with an introduction to phase locked loops (PLLs). This webcast looks at the need for frequency generation; techniques from the past, present, and future; how to assess the performance of a frequency synthesizer; and real world applications. Particular attention will be focused on phase locked loops as frequency synthesizers.
Fundamentals of the RF Transmission and Reception of Digital Signals - Digital Modulation is an important topic for RF designers because most modern day transceivers transmit and receive digitally modulated data. In this webcast, part of ADI's continuing FUNDAMENTALS OF DESIGN series we will introduce you to the challenges—and solutions—for digital modulation. This webcast is a great way for beginners to get introduced to this vital communications standard or for veteran RF designers learn what's new in the field.
Fundamentals of Designing with Semiconductors: Beyond the Op Amp - This webcast, the third of our 12-part series on the Fundamentals of Designing with Semiconductors for Signal-Processing Applications, premieres March 9. It looks at Difference Amps, Instrumentation Amps, Log Amps, and other important amplifiers, and explains when to use each and how to select them for maximum circuit performance.
Fundamentals of Designing with Semiconductors for Signal Processing
Applications: The Op Amp -- In this, the
second webcast of our
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