Performance Optimization of Multichannel Data Acquisition (DAQ) Systems: The Untold Story of the Input Settling Time


In a multichannel, multiplexed data acquisition system, increasing the number of channels per ADC improves the system’s overall cost, area, and power efficiency. The high throughput and energy efficiency of modern, successive approximation register analog-to-digital converters (SAR ADCs) allow system designers to achieve greater channel density than ever before. This article will describe how settling transients at the inputs of the multiplexer, caused by a large scale switching transient at the multiplexer output, requires prolonged acquisition time, effectively decreasing the overall throughput of the multichannel data acquisition system. It will then focus on design trade-offs when minimizing the input settling time, and improving data throughput and system efficiency.

What Is a Multichannel DAQ and How Do We Measure the Performance of a Multichannel DAQ?

A multichannel data acquisition (DAQ) system is a complete signal chain subsystem interfaced to multiple inputs (typically sensors) with the main function of converting the analog signal at the inputs into digital data that a processing unit can comprehend. The main components of a multichannel DAQ system are the analog front-end subsystem (a buffer, a switching element, and signal conditioning block), the analog-to-digital converter (ADC), and the digital interface. For high speed, precision converters, the switching element (typically a multiplexer) is placed before the ADC driver and the converter itself to exploit the advancing performance of modern ADCs. SAR ADCs are the most commonly used type of ADC for these applications due to their combination of speed and precision.

Figure 1
Figure 1. A typical SAR ADC-based, multiplexed data acquisition system block diagram.

High channel density precision DAQ systems for industrial and medical applications aim to compress the largest number of channels into the least possible area. Multiplexed DAQ systems, generally, can achieve high density, high throughput, and good energy efficiency by:

  1. Using a high speed precision SAR ADC
  2. Using the minimum sampling rate per channel
  3. Maximizing the SAR ADC converter utilization where:
Equation 1

with n as the number of channels. The overall throughput of the multichannel data acquisition system, per converter, is given by:

Equation 2

This shows that the overall throughput of the multichannel DAQ system is not only dependent on the speed and resolution of the SAR ADC, but also on how well this converter is utilized.

How Do Delays Affect the Performance of Multichannel DAQ Systems?

In the presence of any settling delays, a term td is added to the actual sampling and conversion period of the ADC, leading to an actual maximum converter sampling rate given by:

Equation 3

wherein TADC is the ADC period per sample (typically found in most ADC data sheets and more commonly the inverse of the SAR ADC sampling rate in seconds per sample). The actual maximum sampling rate of the multichannel DAQ system is always less than the sampling rate of the converter for a non-zero delay td, resulting in a converter utilization that is always less than 100%. From this we can see that any delay that is added to the sampling and conversion period reduces converter utilization. When related to an earlier expression for overall throughput, this effectively reduces the maximum number of channels the multichannel DAQ can accommodate. To summarize, any settling delays decrease the channel density and/or the overall throughput of the multichannel DAQ system.

Now, What Is the Multiplexer Input Switching Glitch and Input Settling Time?

When a multiplexer switches from one input to another, the output still has a memory of the previous input channel in the form of stored charges in the output load capacitance and the parasitic drain capacitance of the multiplexer. This is more evident for highly capacitive loads such as ADC drivers and the ADCs themselves, since there is no low impedance path these stored charges can go. You can even say that these charges are trapped due to the capacitive nature of the output and high impedance of the multiplexer due to the break-before-make (BBM) mechanism of modern multiplexers; they can only be discharged once switched to the next input.

Figure 2
Figure 2. Preswitching state (left), after switching, charge sharing happens, quickly causing voltage drop ∆V (right).

After switching, the input capacitance CA will be connected in parallel to the output capacitance COUT. CA and COUT, however, may initially be at different potentials, which will cause charge sharing between CA and COUT. The charge sharing happens almost instantaneously for very high bandwidth multiplexers, causing a high frequency glitch in the input of the multiplexer. The magnitude of this glitch, V, is given by:

Equation 4

where ∆VC is the difference in capacitor voltages before switching. The transient glitch happening at the input side of the multiplexer is a phenomenon more commonly known as the kickback and is more prevalent for switched applications with highly capacitive loads such as ADCs, capacitive DACs, and sampling circuits to name a few. This subject is briefly illustrated in MT-088. The glitch will have to settle to within 1 LSB of the output to produce valid data for the converter and the time it takes for the input to settle to within 1 LSB (and stay in that range!) is the input settling time (tS). tS is a component of the delay td described earlier, and it may have the most significant contribution to this term.

When ADCs werent as fast as they are today, these glitches and their respective input settling time are insignificant enough to be ignored. However, as ADCs scale their speed, the converter sampling period becomes shorter and shorter, approaching the order of the input settling time. As described earlier, when the ADC period, TADC, is equal to the input settling time tS (and effectively td), the converter utilization is greatly reduced to 50%. This means we’re using only half of what the converter is capable of! Reiterating its significance, the input settling time should start scaling with the speed of the current technology of precision converters, paving the way to advance the performance of multichannel DAQ systems.

How Do We Minimize Input Settling Time?

The switching glitches are usually minimized by using an RC filter between the buffer amplifier and the multiplexer (see CN-0292), known as a snubber network. A signal chain subsystem for a 2-channel, multiplexed analog front-end subsystem and its corresponding switching timing diagram is described in Figure 3.

Figure 3
Figure 3. A 2-channel multiplexed analog front-end subsystem for a multichannel DAQ system and the corresponding timing diagram.

With the snubber RC as the dominant pole, the input glitch and settling transient can be approximated to have a first-order (exponential) response, assuming the multiplexer has a very high bandwidth with respect to the amplifier and snubber RC. To dissect the input glitch further, Figure 4 illustrates the input glitch transient response in detail.

Figure 4
Figure 4. Dissecting the multiplexer input glitch during switching: timing definitions and design goal.

For a first-order assumption, the expression for the error, VERROR, is a decreasing exponential function with respect to time. The initial value (the value at switching) of VERROR is the glitch magnitude ∆V and will die down at a rate depending on the snubber RC values. The time it takes for VERROR to settle to within 1 LSB is defined as the input settling time.

The converter, on the other hand, samples at a period tACQ (also called the acquisition time). At the ADC conversion phase when tACQ elapses, the converter will quantize whatever sampled data is available. This will be problematic if VERROR dies down too slow that it did not settle to within a certain value (1 LSB to a few LSBs). This will cause the current sample to be corrupted by the previous analog input and resulting in cross-talk between the ADC channels. With the input settling time in mind, it is imperative to assure that the input settling time is less than the converter acquisition time to minimize errors. Moreover, further minimizing tS opens up an opportunity to use faster converters to improve the overall throughput and density of the system.

With some math in our repertoire, the expression for the fastest input settling time can be derived at worst case when ∆VC is the full-scale input range and VERROR reaches at least 1 LSB (multiplexer output is within 1 LSB of the target level). The multichannel DAQ system designer will have two design knobs: the snubber time constant and the CA/COUT ratio, thus resulting to an expression for the input settling time:

Equation 5

Here we can see that the input settling time is a linear function of the snubber time constant, τ, and η the number of time constants required for VERROR to settle to within 1 LSB. The most straightforward method to reduce input settling time is to use a low time constant snubber network, which makes sense since faster (high bandwidth) snubber networks will result in lower time constants. This method, however, will present a different set of trade-offs involving noise and loading. Alternatively, we can minimize the term η to achieve similar results.

η is a function of the ratio of the snubber capacitor (CA) to the output capacitor (COUT). The expression can be further simplified if 1 LSB is equal to the full-scale input range divided by 2, raised to the number of bits (N) minus one, and ∆VC is equal to the full-scale input range at worst case.

Equation 6

Equation 6 may not be that intuitive and can be really hard to visualize, so it might be better to just illustrate it with a semilogarithmic graph for 10-, 14-, 18-, and 20-bit resolutions, as given in Figure 5.

Figure 5
Figure 5. A graph of the required time constants to settle to 1 LSB.

It can be seen that higher CA/COUT values result in decreased settling time; even reaching zero-settling time for very high capacitor ratios. Since COUT is essentially the drain capacitor of the multiplexer and input capacitances of succeeding stages, only CA remains as the more versatile degree of freedom. The zero settling time for a 10-bit resolution requires the CA to be at least 1000× larger than COUT and a whopping 1,000,000× larger than COUT for 20-bit systems! For perspective, a typical load of 100 pF requires snubber capacitors of 100 nF and 100 µF for 10- and 20-bit systems, respectively, to achieve zero settling time.

In summary, minimizing the input settling time can be achieved through two methods:

  1. Using high bandwidth for the snubber network
  2. Using high values of CA with respect to COUT

High Bandwidth and a Large Snubber Capacitor Minimizes Input Settling Time, So Let’s Just Use the Highest Bandwidth and Largest Capacitor

No! You must consider the RC loading effects and the amplifier’s driving capability! In order to investigate the loading effects of the snubber network to the buffer amplifier, the analog front-end subsystem should be analyzed in the frequency domain.

Since we are building on the idea of first-order response for the input glitch, the snubber network pole should be the most dominant contributor. In other words, the snubber bandwidth should be less than both the buffer amplifier and the multiplexer to avoid multiple poles interacting, ensuring that the first-order approximation will hold.

Figure 6
Figure 6. The buffer and snubber equivalent circuit (left) and the equivalent impedance of the amplifier and snubber network (right).

A typical buffer architecture consists of a precision amplifier in a buffer (G = 1) configuration in cascade with the snubber network. Analyzing in the frequency domain, the output of this subsystem depends on the ratio of the snubber input impedance to the sum of the snubber input impedance and amplifier closed-loop output impedance. By inspection, the snubber input impedance should be greater than the amplifier’s closed-loop impedance to avoid loading effects, which is described in Equation 7.

Equation 7

That is, to avoid the snubber network loading the buffer amplifier, we should:

  1. Increase the snubber time constant, RACA, effectively decreasing the bandwidth
  2. Use small snubber capacitor CA
  3. Choose an amplifier with very low closed-loop output impedance

The first two options provide us with a clear understanding of the trade-offs between the loading effects and input settling time. This puts a limit on how high we can go with the snubber bandwidth and capacitor. The third option introduces a performance parameter that should be taken into account when choosing the appropriate precision amplifier. Stability and driving capabilities should also be considered.

Figure 7 shows that for a precision amplifier that has enough bandwidthsay the ADA4096-2 with –3 dB closed-loop bandwidth of about 970 kHzthe results agree with the analysis presented so far, with the exception of a few waveforms. For a snubber bandwidth of 10 kHz, the largest CA resulted in the fastest input settling time. While for a snubber bandwidth of 200 kHz, increasing CA still results in faster settling time until loading takes effect. The underdamped response seen from the results features the minimum glitch magnitude but has longer settling time than the response from the smaller CA, despite higher glitch magnitude. This stresses the importance of carefully investigating how the snubber loads the amplifier, as this should always be taken into account when choosing the components for the system.

Figure 7
Figure 7. Multiplexer input for snubber bandwidth of 10 kHz (top) and 200 kHz (bottom) for ADA4096-2 amplifier model.

As presented earlier, one amplifier parameter to look at is the closed-loop output impedance. An operational amplifier typically has its closed-loop impedance inversely proportional to its open-loop gain AV. We also want a high bandwidth for the snubber network for minimum settling time, requiring the amplifier to have a 3 dB bandwidth even greater than the snubber bandwidth. Aside from low noise, offset, and offset drift, a precision amplifier that is the most suited for use in multiplexed DAQ system for minimum input settling time has two more prioritized attributes: 1) has high bandwidth and 2) has very low closed-loop impedance. However, these do not come without trade-offs and they are in the form of power consumption. As examples, we can look at the closed-loop impedances of both the ADA4096-2, and ADA4522-2, shown in Figure 8.

Figure 8a
Figure 8a. Data sheet plots of the closed-loop impedance for ADA4522-2.
Figure 8b
Figure 8b. Data sheet plots of the closed-loop impedance for ADA4096-2.

From the data sheet plots of the closed-loop output impedances, and with ADA4522-2’s 3 dB closed-loop bandwidth of 6 MHz (at nominal), it is clear that it is the more suitable driver for the application. But when power consumption is prioritized, ADA4096-2’s with supply current of 60 µA per amplifier (at typical) is more attractive than ADA4522-2’s 830 µA per amplifier (at typical). Nonetheless, both precision amplifiers can be used; it all just boils down on what the application really needs.


Alright, So What’s the Best That We Can Do?

To maximize the density and throughput of multichannel DAQ systems, the input settling time should be less than or equal to the ADC acquisition time. Any additional delay diminishes the performance of multichannel DAQ systems. Minimizing the input settling time involves increasing the bandwidth and the capacitor of the snubber network, though care must be exercised when choosing component values due to loading effects in the frequency domain. Finally, selecting the most appropriate precision amplifier involves balancing the trade-off between power, closed-loop output impedance, and the 3 dB bandwidth, prioritizing what the application really requires.


Corrigan, T. Application Note,  How to Calculate the Settling Time and Sampling Rate of a Multiplexer. Analog Devices, Inc., 2009.

Interactive Design Tool: Analog Switch Settling-Time Calculator. Analog Devices, Inc.

MT-088 Tutorial, Analog Switches and Multiplexers Basics. Analog Devices, Inc., 2009. 


Dan Burton, Vicky Wong, Peter Ohlon, Eric Carty, Rob Kiely, May Porley, Jess Espiritu, Jof Santillan, Patrice Legaspi, Peter Hurrell, and Sherwin Almazan.


Joseph Leandro Peje

Joseph Leandro Peje

Joseph Leandro Peje received his B.S. degree in computer engineering from the University of the Philippines—Diliman, Quezon City, Philippines; and is finishing up his Master’s in electrical engineering, with a concentration in microelectronics, at the same university. He is currently an analog IC design engineer at Analog Devices in General Trias, Philippines, focusing on precision amplifiers and analog and mixed-signal systems verification.