Follow Us With each new generation, performance improvements are often accompanied by practical requirements the user must adhere to for the best performance from an op amp or a converter. Older-generation op amps often required external compensation to tailor response; flash A/Ds are fast but are power-hungry and have low input impedance. BiMOS converters simplify applications issues; the typically high-impedance, benign input structures are easy to drive. High-speed CB op amps and CMOS, switched-capacitor-based converters minimize power consumption and price. An application where an AD8011 op amp drives an AD876 A/D shows strengths and practical issues of new-generation ICs.
High-speed, switched-capacitor A/D architectures require the user to understand a unique set of issues when designing interface circuitry. The optimum interface depends on whether the application requires only low distortion and spurs (dynamic characteristics), low noise, or both low noise and low distortion.
- Systems where the entire signal chain (series of functional elements that process the signal) must optimize specs like total harmonic distortion (THD) and spurious-free dynamic range (SFDR)—for example, communications systems—typically involve spectral analysis or processing. Input signals change in relatively small increments between samples; signal content is confined to < Nyquist frequency (i.e., 1/2 the sampling rate).
- Systems focused on noise performance may sacrifice THD and SFDR to increase dynamic range (SNR). Though distortion specifications may not be as important in these low-noise applications (such as CCD-based imaging), wide bandwidth and fast transient response may be needed to insure fast settling.
- Data-acquisition systems, such as DSOs-digital sampling oscilloscopes-typify applications that require both low spurs & distortion and wide dynamic range (SNR). Besides voltage and current noise, phase noise, such as that generated from aperture jitter, is of concern. These systems often deal with a wide variety of signals, performing spectral signal processing and handling large-scale transients (typically from multiplexed front-ends).
Driving switched-capacitance ADC inputs: The input hold capacitor of the AD876 must be charged to the new input voltage each clock cycle. The amount of charge the input driver must supply depends on the difference between the voltage stored on the hold capacitor from the previous conversion and the voltage applied to the A/D when the sample clock transitions from high (hold mode) to low (track). The smaller this difference, the less incremental charge is needed. On the other hand, for a full-scale change between conversions, the input driver must supply a large increment of charge. The circuit of Figure 2, with an AD8011 driving the AD876, illustrates performance options. Regardless of how the op amp itself is configured, adding a series resistor (and possibly a shunt capacitor) can improve performance of the op amp/converter pair.
To examine some of the considerations for selecting optimum-value resistors and capacitors for a particular application, the AD8011 was configured in a gain of +2 (bandwidth of about 180 MHz) and connected to the AD876 input as shown.
Figure 3a shows the test signals: The top trace is the analog input to the AD8011, a 1-V p-p square-wave. The bottom trace is the AD876 sample clock. When the clock is low, the SHA tracks the input; when it goes high, the A/D's SHA switches to Hold. Note that the AD876 must acquire a full-scale change in input voltage each conversion; this condition places the most severe demands on the AD8011, since it must supply the maximum amount of charge each conversion period. The AD8011 cannot supply the difference in charge instantaneously, so there are transients at the converter's input during the transitions of the A/D sample clock.
Figure 3b shows the transients while the input square wave is at its positive excursion on an expanded scale (upper plot), with the 25-ns track-mode clock pulse. The smaller rising-edge hold transient is unimportant; it occurs long before the next sample is taken. The falling-edge transient, as the ADC acquires the full-scale charge change, is about -114 mV; recovery and settling to 0.1% (10 bits or 2 mV) must take place within the duration of the track-mode pulse and prior to the rising edge-here, it occurs in 20 ns with a 100-Ω resistor. For a 20-MSPS sample rate (50% duty cycle), recovery must be within 25 ns. A slower amplifier could be used for lower sample rates.
Series resistors help: Most applications benefit from series resistance between the AD8011's output and the AD876's VIN pin to isolate the output stage of the AD8011 from the input capacitance of the AD876, and to limit the peak current the op amp must supply. As little as 33 Ω (Figure 4a) greatly reduces THD (from -47 to -64 dB) and increases SNR (from 58 to 60 dB) and SFDR (from 48 to 68 dB); up to 500 Ω can be used without increasing distortion due to the nonlinear capacitive load. Settling time is also improved by small series resistance; without it, the ADC's capacitive load directly applied at the amplifier's output causes some peaking in the amplifier's response and slower settling. But increased resistance—considering the ADC's input capacitance, strays, and any added capacitance—reduces band-width through low-pass filtering. 500 Ω and 20 pF has a -3-dB frequency of about 16 MHz.
Shunt Capacitance Limits Noise: The AD876 has a full-power bandwidth of at least 150 MHz and an even greater noise bandwidth. Wideband incoming noise at frequencies > 1/2 the sampling rate will be aliased back to baseband and will decrease the SNR of the digitized signal. For noise-sensitive applications, a shunt capacitor, with the series resistor (Figure 2) provides filtering of high-frequency external noise at the AD876 input.
Figure 4b shows noise and distortion using a 100-Ω series resistor and various shunt capacitances. SFDR is relatively unaffected, holding in the 66 to 68-dB range. However, for capacitances in the range from 50 pF to 200 pF, THD increases substantially (from -65 to -62 dB) and SNR decreases substantially (from 59 to as low as 52 dB). The reduced SNR is caused by aliasing of high-order harmonics due to glitching of the not-quite-settled hold-to-track transient; they show up as noise in the baseband signal at the output of the AD876 under the conditions of 4b.
For higher values of shunt capacitance, the SNR greatly improves, but at the cost of bandwidth. With (say) 200 pF, the overall system -3-dB bandwidth decreases to about 8 MHz—and any fast transients in the input signal may not settle to 10-bit accuracy in a single conversion period.
When using series R and shunt C to optimize system behavior, it is important to take into account the application's goals. If dynamic performance is paramount over a wide range of input frequencies, it is probably best to keep the shunt capacitance below 20 pF with a 100-Ω series resistor. If you want to optimize noise performance, consider longer RC time constants and whether transient response can be traded for low noise. In any case, best performance occurs when the input is given time to settle to 10-bit accuracy prior to the track-to-hold transition of the AD876 sample clock. Keep in mind also that the AD8011 is so quiet that wideband noise can be filtered at an earlier stage without concern that AD8011 noise will degrade SNR.
