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Heterodyne radios, such as the ADF7024 transceiver, use a mixer to downconvert received radio frequency (RF) signals to an intermediate frequency (IF). Interfering signals, called interferers, that lay on the image frequency are also mixed down to the wanted frequency. The interfering signals desensitize the receiver, resulting in blocking on the wanted channel. In theory, an ideal transceiver that employs an IQ receive architecture can be configured to prevent the image frequency from mixing onto the wanted channel. This assumes that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. This 6-page Application Note describes the fully autonomous image rejection (IR) calibration firmware download module for the ADF7024 transceiver IC.
This 4-page Application Note describes a protocol for programming the flash memory in the ADuMC320 precision analog microcontroller, which incorporates high performance analog and digital peripherals, an ARM Cortex-M3 processor, and flash memory. Its MDIO interface can operate at up to 4 MHz, simultaneously executing from one flash block and writing/erasing the other flash block.
This 8-page Application Note describes a reference design that improves the overall link budget by extending the range of the ADF7023 ISM band transceiver by almost 20 dB. In a non-interference-limited line-of-sight scenario, this equates to a range increase of approximately six to seven times. The design, which consists of an ADF7023 transceiver and an RFFM6901 front-end module, is suitable for operation in the 902 MHz to 928 MHz ISM band and complies with FCC regulations.
The evaluation board for the AD9129 14-bit, 5.6-GSPS RF digital-to-analog converter uses power supply filters to guarantee optimal performance. This 3-page Application Note explores the effects of removing most of the filter components. All ferrite beads on the board were removed, as well as the majority of the capacitors on the power supplies. Phase noise, noise spectral density (NSD), spurious-free dynamic range (SFDR), intermodulation distortion (IMD), and adjacent channel leakage ratio (ACLR) performance were all measured to demonstrate the effect of removing the filter components. The measurement results showed that the ferrite beads improved close-in phase noise at 20 Hz offset by approximately 5 dB, as well as single-tone IMD by up to 5 dB. Most of the capacitors proved to be redundant, however. The decoupling capacitors improved the ACLR for 6 MHz carriers by 5 dB; and the capacitor arrays improved the ACLR for 6 MHz carriers by approximately 6 dB and the NSD by approximately 1 dB. Removing all of the other the capacitors did not affect the performance.
This 7-page Application Note describes the Reed-Solomon firmware module, which contains both forward error correction and advanced encryption standard (AES) encryption, for the ADF7023 transceiver. Reed-Solomon encoding appends check symbols to the transmitted data. When received, these symbols detect the presence of errors and correct them in the received data. The firmware module is flexible, allowing the user to select values that enable correction of up to five error bytes within a packet. Encoded packets are resilient to burst and random errors; their coding gain improves link margin.
This 11-page Application Note describes the radio performance of the ADF7021-N transceiver when configured for operation according to the wireless meter-bus (WM-Bus) standard, focusing on key receiver parameters applicable to the 2.4 kbps and 4.8 kbps modes of operation. These parameters are packet error rate (PER) over power, sensitivity over carrier frequency error, blocking, and adjacent channel selectivity.
Heterodyne radios, such as the ADF7023 family of transceivers, use a mixer to downconvert received radio frequency (RF) signals to an intermediate frequency (IF). Interfering signals, called interferers, that lay on the image frequency are also mixed down to the wanted frequency. This desensitizes the receiver, resulting in blocking on the wanted channel. In theory, an ideal transceiver, which employs an IQ receive architecture, can be configured to eliminate the image frequency mixing onto the wanted channel. This theory assumes that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a firmware download module, until the quadrature signals are optimally balanced, providing maximum image rejection. This 6-page Application Note describes the fully autonomous image rejection (IR) calibration firmware download module for the ADF7023 transceiver IC. With minimum user input, this firmware optimizes the image rejection with a default configuration completely autonomously.
This 4-page Application Note provides information on the built-in packet error rate (PER) test mode on the ADF7023 and ADF7023-J. This mode helps the user to set up a communication link and test its quality. Up to 65,535 packets can be transmitted with a programmable delay between packets. The packet stored in packet RAM is transmitted each time. If the cyclic redundancy check (CRC) is correct, the receiver determines it has correctly received a packet.
When the ADF7023 receives a packet in packet mode, it stores the data in a linear sequence in the packet RAM. Prior to transmission, the data to be transmitted is written to the packet RAM in a linear sequence, as described in the ADF7023 data sheet. The ADF7023 packet RAM is 240 bytes long. If the packet length is greater than 240 bytes, additional measures are required. This 4-page Application Note describes a method for handling longer packet lengths on the ADF7023, up to a maximum length of 65,535 bytes, via a rolling buffer mechanism. This method reuses and renames several registers of the ADF7023.
This 11-page Application Note describes a reference design using the ADF7241/ADF7242 highly integrated, low power, high performance transceiver and the SE2431L fully integrated RF front-end. The ADF7241 and ADF7242, which operate in the global 2.4-GHz ISM band, provides flexibility, robustness, ease of use, and low current consumption. They support the IEEE 802.15.4-2006 2.4‑GHz PHY requirements. The ADF7242 also supports proprietary GFSK/FSK/GMSK/MSK modulation schemes in both packet and data streaming modes. The Skyworks SE2431L, designed for 2.4 GHz applications, provides ease of use and maximum flexibility, with fully matched 50 Ω input and output, integrated interstage matching, harmonic filter, and digital controls that are compatible with 1.6 V to 3.6 V CMOS levels.
Heterodyne radios, such as the ADF7021 family of transceivers, use a mixer to down convert received RF signals to an intermediate frequency (IF). The output of the mixer contains the wanted frequency component along with an unwanted component at the image frequency. Unwanted signals present at the image frequency can degrade receiver sensitivity, resulting in loss of signal on the wanted channel. In theory, transceivers employing an I/Q receive architecture can be configured to infinitely reject the image frequency, assuming that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a digital control register until the quadrature signals are optimally balanced, providing maximum image rejection. This 11-page Application Note provides information on the mechanism that generates the image frequency and describes how image calibration can be implemented on the ADF7021, ADF7021-N, and ADF7021-V.
This frequency selective, radio frequency (RF) detector offers a 90-dB detection range from 35 MHz to 4.4 GHz. Unlike a standalone detector that does not discriminate between signals in the frequency spectrum, this circuit can focus on a narrow band of frequencies, enhancing performance over the specified range. The rms responding circuit is stable vs. temperature and frequency, making it attractive for applications that require precise frequency control, selective RF power measurement, and strong immunity to unwanted blockers.
This true rms responding power detector uses a variable gain amplifier (VGA) and a power detector to provide a 95-dB wide detection range, making it useful for accurate measurement of signals with diverse or varying crest factors, such as those found in GSM/EDGE, CDMA, WCDMA, TD-SCDMA, and LTE receivers and transmitters. The 65-dB detection range of the ADL5902 rms detector is extended to 95 dB by the addition of the AD8368 linear-in-dB VGA.
This flexible, frequency agile, direct conversion IF-to-baseband receiver features a fixed 5-dB conversion gain to reduce the cascaded noise figure. Variable baseband gain adjusts the signal level, and a programmable low-pass filter eliminates out-of-channel blockers and noise. The filter bandwidth can be dynamically adjusted as the input signal bandwidth changes, ensuring full use of the available dynamic range of the driven ADC. The core circuit is an integrated I/Q demodulator with fractional-N PLL and VCO. With a single variable reference frequency, the PLL/VCO can provide a local oscillator (LO) between 750 MHz and 1150 MHz.
This broadband direct-conversion transmitter (analog baseband in, RF out) supports RF frequencies from 30 MHz to 2.2 GHz using a phase-locked loop (PLL) with an on-chip broadband voltage-controlled oscillator (VCO). Unlike modulators that use a divide-by-1 local oscillator (LO) stage, harmonic filtering of the LO is not required as long as the LO inputs to the modulator are driven differentially. The ADF4351 provides differential RF outputs and is, therefore, an excellent match. This PLL-to-modulator interface is useful for all I/Q modulators and I/Q demodulators that contain a 2XLO-based phase splitter.
This 75-MHz low-power (25 mW total) direct digital synthesis (DDS) waveform generator includes an output buffer and anti-imaging filter to provide improved spectral performance, making it suitable for frequency generation or clocking applications requiring sine wave, triangular wave, and square outputs up to 18 MHz. As sampled data devices, low-power DDS devices must be followed by a suitable anti-imaging filter to remove spectral images, but their maximum current output is approximately 4 mA into a recommended 200-Ω load, so an op amp buffer at the DDS output is required to provide a low-impedance drive source for a high-quality 50-Ω filter. The combination of the DDS, output buffer, and seventh-order elliptic low pass filter provides high-quality spectral performance.
This PLL circuit uses a 13-GHz fractional-N synthesizer, wideband active loop filter, and VCO, to achieve phase settling time of less than 5 μs to within 5° for a 200-MHz frequency jump. The performance is achieved using an active loop filter with 2.4-MHz bandwidth. This wideband loop filter is enabled by the 110-MHz maximum frequency of the ADF4159’s phase-frequency detector (PFD); and the 145-MHz gain-bandwidth product of the AD8065 op amp. The AD8065 can operate on a 24 V supply voltage, allowing control of most wideband VCOs having tuning voltages from 0 V to 18 V.
Dual 105-MHz, low-noise, low-power, low-drift Operational Amplifier
The ADA4805-2 high-speed dual op amp offers rail-to-rail outputs, 125-μV maximum input offset voltage, 105-MHz unity-gain bandwidth, 160-V/μs slew rate, 5.9-nV/√Hz voltage noise, and 0.6-pA/√Hz current noise, making it ideal for low-power, high-resolution data-acquisition systems. Its 500-µA quiescent current per amplifier is reduced to 3 µA in shutdown mode; the output settles to 16 bits within 3 µs from shutdown to fully on, allowing the amplifier to be turned off between ADC samples. The ADA4805-2 operates on a single 2.7-V to 10-V supply or dual ±1.35-V to ±5-V supplies. Available in an 8-lead MSOP package, it is specified from –40°C to +125°C and priced at $1.64 in 1000s.
Dual, 11-/16-bit, 2.8-GSPS, TxDAC+® Digital-to-Analog Converters
AD9135/AD9136 dual 11-/16-bit, 2.8-GSPS
digital-to-analog converters (DACs) enable multicarrier generation up to the
Nyquist frequency. The low-distortion design specifies 82-dBc spurious-free
dynamic range (SFDR), 90‑dBc intermodulation distortion (IMD), and
Ultralow-noise Linear Regulator provides 600 mA, high PSRR
The ADM7154 linear regulator operates from 2.3 V to 5.5 V and provides up to 600 mA of output current with high power supply rejection, ultralow noise, and excellent line- and load transient response with only a 10 µF ceramic output capacitor. It is available in a variety of fixed output voltage options from 1.2 V to 3.3 V, with 0.9-μV rms typical output noise from 100 Hz to 100 kHz, and 1.5-nV/√Hz noise spectral density from 10 kHz to 1 MHz. Available in an 8-lead LFCSP and SOIC packages, the ADM7154 is specified from –40°C to +125°C and priced from $2.14 in 1000s.
Ethernet/Gigabit Ethernet Clock Generator
The AD9574 multiple output clock generator comprises a dedicated phase-locked loop (PLL) core optimized for Ethernet and gigabit Ethernet line card applications. The high-performance, low-jitter integer-N PLL frequency synthesizer maximizes network performance. Configuration for a particular application is accomplished by connecting external pull-up or pull-down resistors to the program reader pins to establish frequency translations, clock output functionality, and input reference functionality. Connecting an external oscillator to one or both of the reference inputs results in a set of output frequencies as determined by the configuration. A stable clock source connected to the monitor clock input enables reference quality of service (QoS) status monitoring. The PLL consists of a low-noise phase-frequency detector (PFD), a precision charge pump (CP), a partially integrated loop filter (LF), a low phase noise voltage-controlled oscillator (VCO), and feedback and output dividers. The integrated loop filter requires only one external capacitor connected to the LF pin. Operating on a 2.97-V to 3.63-V supply, the AD9574 dissipates 698 mW with all blocks running, 569 mW in a typical configuration, and 422 mW in a minimal power configuration. Available in a 48-lead LFCSP package, it is specified from –40°C to +85°C and priced at $5.10 in 1000s.
Synchronous Demodulator and Configurable Analog Filter
The ADA2200 synchronous demodulator and configurable analog filter performs precision magnitude and phase measurements in low power sensor signal conditioning and data acquisition applications. Using sampled analog technology (SAT), the analog input, sampled analog output, device includes a low-pass 1/8× decimation finite impulse response (FIR) filter, a configurable infinite impulse response (IIR) filter, a mixer with 0°/90° phase selection, a reference clock, and an ADC driver output. All signal processing is performed in the analog domain, eliminating the effects of quantization noise and rounding errors, reducing downstream ADC sample rates, and offloading tasks from the digital processor. When the demodulation function is disabled, the device acts as a precision filter with programmable bandwidth and tunable center frequency. Single-ended and differential signal interfaces are possible on both input and output terminals, simplifying connection to other components. The low power consumption and rail-to-rail operation are ideal for battery-powered and low-voltage systems. On-chip clock generation produces a mixing signal with programmable frequency and phase. In addition, output signal synchronization eases interfacing to converters, multiplexers, and other sampled systems. Operating on a 2.7-V to 3.6-V supply, the ADA2200 draws 395 µA. Available in a 16-lead TSSOP package, it is specified from –40°C to +85°C and priced at $2.95 in 1000s.
Wideband Quadrature Modulator includes fractional-N PLL and four VCOs
The ADRF6720-27 wideband quadrature modulator with integrated synthesizer is ideally suited for 3G and 4G communication systems. Comprising a high-linearity broadband modulator, fractional-N phase-locked loop, and four low-phase-noise multicore VCOs, it offers digital programmability for carrier feedthrough optimization, sideband suppression, HD3/IP3 optimization, and high-side or low-side LO injection. The local oscillator (LO) can be generated externally, or internally via the on-chip integer-N and fractional-N-synthesizers. The multicore VCOs enable LO coverage from 356.25 MHz to 2855 MHz. Quadrature signals are generated with a divide-by-2 phase splitter or with a polyphase filter. Operating on a 3.3 V supply, the ADRF6720-27 draws 425 mA with the modulator enabled, 218 mA with the modulator disabled, and 14.5 mA in power-down mode. Available in a 40-lead LFCSP package, it is specified from –40°C to +85°C and priced at $7.95 in 1000s.
24-bit, 250-kSPS Sigma-Delta ADC with 20-μs settling and rail-to-rail buffers
The AD7175-2 low-noise multiplexed Σ-Δ analog-to-digital converter accepts two fully differential or four pseudo-differential low-bandwidth inputs. The fast settling design has a maximum 50-kSPS channel scan rate and 5-SPS to 250-kSPS output data rates. The integrated analog- and digital signal conditioning blocks allow individual configuration for each input channel. True rail-to-rail buffers on the analog- and external reference inputs provide easy to drive high-impedance inputs. The precision 2.5-V low-drift (2 ppm/°C) reference and reference buffer add functionality and reduce external component count. The digital filter allows simultaneous 50/60 Hz rejection at 27.27 SPS output data rate. The ADC automatically cycles through each selected channel. Further digital processing functions include offset and gain calibration. Operating with +5-V and ±2.5-V supplies, the AD7175-2 dissipates 105 mW with buffers enabled, internal clock, and internal reference; 42 mW with buffers disabled, external clock, and external reference; 125 µW in standby mode, and 25 µW in power-down mode. Available in a 24-lead TSSOP package, it is specified from –40°C to +105°C and priced at $11.85 in 1000s.
4-input, 4-output, Adaptive Clock Translator for multiservice line cards
The AD9554-1 low-loop-bandwidth clock translator provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). It generates an output clock synchronized to up to four external input references. The digital PLL (DPLL) reduces input time jitter and phase noise associated with the external references. The digitally controlled loop and holdover circuitry continues to generate a low-jitter output clock even when all reference inputs have failed. Four differential clock outputs at frequencies from 430 kHz to 941 MHz are individually configurable for HCSL-, LVDS-, or LVPECL compatibility. The devices support GR-1244 Stratum 3 stability in holdover mode, Telcordia GR‑253 jitter specifications in up to OC-192 systems, and ITU-T G.8262 synchronous Ethernet slave clocks. Operating on 1.8-V and 3.3-V supplies, the AD9554-1 dissipates 920 mW in typical configurations and 164 mW in power-down mode. Available in a 56-lead LFCSP packages, it is specified from –40°C to +85°C and priced at $20.81 in 1000s.
Dual digitally controlled RF VGA operates from 100 MHz to 4000 MHz
ADRF6573 dual high-performance, digitally
controlled, variable-gain amplifier (VGA) operates from 100 MHz to 4000 MHz.
Each channel includes a 6-bit digital step attenuator (DSA) with a 31.5-dB
gain control range, 0.5-dB steps, and
Duncan Bosworth, Multiband military communications challenges overcome by software-defined radio, Miltary Embedded Systems, 2014-10-03
Ryan Curran, Qui Luu, and Maithil Pachchigar, RF-to-Bits Solution Offers Precise Phase and Magnitude Data for Material Analysis, Analog Dialogue, 2014-10-01
Bob Clarke and Kevin Kreitzer, Maximising the dynamic range of software defined radio, Electronic Product Design & Test, 2014-10-01
Rob Reeder, Design Wideband Front Ends for GSPS Converters, Electronics Maker, 2014-09-23
Duncan Bosworth, Software defined radio in the battlefield: Multiband analogue front end brings one chip radio closer to reality, New Electronics, 2014-09-09
Ian Beavers, Gigasample ADCs Promise Direct RF Conversion, Electronic Design, 2014-08-27
Rob Reeder, GSPS Converter Wideband Front-End Design, DigiKey, 2014-05-28
Ian Beavers, Understanding Spurious-Free Dynamic Range In Wideband GSPS ADCs, Electronic Design, 2014-05-12
Qui Luu and Benjamin Sam, Differential Drive Optimizes Active Mixers, Microwaves&RF, 2014-04-11
Tom Gratzek, Product How-to: Sophisticated tools accelerate SDR exploration, EDN, 2014-04-08
Jarrett Liner, Understanding and designing wideband output networks for high speed D/A converters, EDN, 2014-03-19
Rob Reeder, Design Wideband Front Ends for GSPS Converters, Electronic Design, 2014-01-24
Kyle Slightom, Dual-Loop Clock Generator Cleans Jitter, Provides Multiple High-Frequency Outputs, Analog Dialogue, 2014-01-06
Duncan Bosworth, Multiband Analog Front End Brings One-Chip Radio Closer to Reality, Microwave Engineering Europe, 2013-12-02
Duncan Bosworth, Multiband Analogue Front End Brings One-Chip Radio Closer to Reality, EDN Europe, 2013-11-29
Jonathan Harris, Interleaving Spurs: Let’s Look at the Math, Planet Analog, 2013-09-17
Ray Sun, How to Design and Debug a Phase-Locked Loop (PLL) Circuit, Analog Dialogue, 2013-09-04
Interfacing GSPS Data Converters to FPGAs - A new generation of high-performance GSPS data converters are poised to simplify wideband RF architectures and greatly enhance system capabilities. This webcast explores the conversion technology as featured on a reference design and quick-start FPGA-friendly prototyping module. Topics covered include: GSPS ADC and DAC IC technology, an overview of the JESD204B interface, and the software that makes the converters and FPGA work together seamlessly.
Developing Multiple-Input Multiple-Output (MIMO) Systems with the AD9361 - As software defined radio (SDR) and multiple-input multiple-output (MIMO) become more prevalent, there is a need for more channel diversity. This webcast will detail how to use multiple AD9361 RF agile transceivers to create an N×N MIMO system, as well as explore the available tradeoffs in the design. The AD9361 is a fully integrated 2×2 MIMO transceiver. Its programmability and wideband capability make it ideal for a broad range of transceiver applications.
Digital Filter Design for Integrated RF Transceivers - This webcast introduces how MATLAB from MathWorks can be used for complicated filter design in wireless SDR systems and components. We will create a model of the Analog Devices AD9361 and AD9364 RF transceivers, as integrated on the AD-FMCOMMS2-EBZ and AD-FMCOMMS4-EBZ SDR development platforms. We will use that model to design a filter for the internal FIR filters using the generated coefficients in an example system design.
Integrated Software-Defined Radio on Zynq®-7000 All Programmable SoC -- This course introduces wireless communication system design on the new Avnet Zynq®-7000 All Programmable SoC/AD9361 Software-Defined Radio Evaluation Kit featuring Analog Devices AD9361 single-chip RF agile transceiver. An IEEE 802.11 receiver example will demonstrate system-level simulation using MATLAB® and Simulink® modeling and code generation tools from MathWorks. Using the Xilinx Vivado® Design Suite, the system will be implemented for production showing the receiver detecting 802.11 beacon frames in a stand-alone system running UBUNTU desktop Linux on Xilinx Zynq AP SoC. Presentations will alternate with instructor-led demos to illustrate coding techniques within MathWorks and Xilinx development tools for high-speed digital signal processing.
Solving the Elusive Baseband to Antenna Problem using RFDAC Technology - This webinar will explore RF transmitter architectures, concentrating on the direct-to-RF architecture enabled by RFDAC technology. Aspects of the direct-to-RF transmitter system design will be explored including gain, signal bandwidth, digital signal processing requirements, frequency planning, thermal noise, clock synthesis + phase noise, harmonics, sampling images, pre-distortion techniques, and deterministic latency.
The Evolving Architecture of Military Communication Systems -- This webcast explores the different bands of Military Communications, and the advantages and disadvantages of each. We talk briefly about the shift toward software defined radios (SDR) and what that means for today’s system designers. We talk about traditional Tx/Rx signal chains for these radios, where they are heading in the future, and the key analog and mixed-signal technology that is driving these changes.
Fundamentals of Data Conversion in Receivers - This webinar examines a contemporary receive signal chain and takes a close look at selecting suitable data converters, their key specifications, and the tradeoffs that must be made.
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