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This 4-page Application Note describes a protocol for programming the flash memory in the ADuMC320 precision analog microcontroller, which incorporates high performance analog and digital peripherals, an ARM Cortex-M3 processor, and flash memory. Its MDIO interface can operate at up to 4 MHz, simultaneously executing from one flash block and writing/erasing the other flash block.
This 8-page Application Note describes a reference design that improves the overall link budget by extending the range of the ADF7023 ISM band transceiver by almost 20 dB. In a non-interference-limited line-of-sight scenario, this equates to a range increase of approximately six to seven times. The design, which consists of an ADF7023 transceiver and an RFFM6901 front-end module, is suitable for operation in the 902 MHz to 928 MHz ISM band and complies with FCC regulations.
The evaluation board for the AD9129 14-bit, 5.6-GSPS RF digital-to-analog converter uses power supply filters to guarantee optimal performance. This 3-page Application Note explores the effects of removing most of the filter components. All ferrite beads on the board were removed, as well as the majority of the capacitors on the power supplies. Phase noise, noise spectral density (NSD), spurious-free dynamic range (SFDR), intermodulation distortion (IMD), and adjacent channel leakage ratio (ACLR) performance were all measured to demonstrate the effect of removing the filter components. The measurement results showed that the ferrite beads improved close-in phase noise at 20 Hz offset by approximately 5 dB, as well as single-tone IMD by up to 5 dB. Most of the capacitors proved to be redundant, however. The decoupling capacitors improved the ACLR for 6 MHz carriers by 5 dB; and the capacitor arrays improved the ACLR for 6 MHz carriers by approximately 6 dB and the NSD by approximately 1 dB. Removing all of the other the capacitors did not affect the performance.
This 7-page Application Note describes the Reed-Solomon firmware module, which contains both forward error correction and advanced encryption standard (AES) encryption, for the ADF7023 transceiver. Reed-Solomon encoding appends check symbols to the transmitted data. When received, these symbols detect the presence of errors and correct them in the received data. The firmware module is flexible, allowing the user to select values that enable correction of up to five error bytes within a packet. Encoded packets are resilient to burst and random errors; their coding gain improves link margin.
This 11-page Application Note describes the radio performance of the ADF7021-N transceiver when configured for operation according to the wireless meter-bus (WM-Bus) standard, focusing on key receiver parameters applicable to the 2.4 kbps and 4.8 kbps modes of operation. These parameters are packet error rate (PER) over power, sensitivity over carrier frequency error, blocking, and adjacent channel selectivity.
Heterodyne radios, such as the ADF7023 family of transceivers, use a mixer to downconvert received radio frequency (RF) signals to an intermediate frequency (IF). Interfering signals, called interferers, that lay on the image frequency are also mixed down to the wanted frequency. This desensitizes the receiver, resulting in blocking on the wanted channel. In theory, an ideal transceiver, which employs an IQ receive architecture, can be configured to eliminate the image frequency mixing onto the wanted channel. This theory assumes that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a firmware download module, until the quadrature signals are optimally balanced, providing maximum image rejection. This 6-page Application Note describes the fully autonomous image rejection (IR) calibration firmware download module for the ADF7023 transceiver IC. With minimum user input, this firmware optimizes the image rejection with a default configuration completely autonomously.
This 4-page Application Note provides information on the built-in packet error rate (PER) test mode on the ADF7023 and ADF7023-J. This mode helps the user to set up a communication link and test its quality. Up to 65,535 packets can be transmitted with a programmable delay between packets. The packet stored in packet RAM is transmitted each time. If the cyclic redundancy check (CRC) is correct, the receiver determines it has correctly received a packet.
When the ADF7023 receives a packet in packet mode, it stores the data in a linear sequence in the packet RAM. Prior to transmission, the data to be transmitted is written to the packet RAM in a linear sequence, as described in the ADF7023 data sheet. The ADF7023 packet RAM is 240 bytes long. If the packet length is greater than 240 bytes, additional measures are required. This 4-page Application Note describes a method for handling longer packet lengths on the ADF7023, up to a maximum length of 65,535 bytes, via a rolling buffer mechanism. This method reuses and renames several registers of the ADF7023.
This 11-page Application Note describes a reference design using the ADF7241/ADF7242 highly integrated, low power, high performance transceiver and the SE2431L fully integrated RF front-end. The ADF7241 and ADF7242, which operate in the global 2.4-GHz ISM band, provides flexibility, robustness, ease of use, and low current consumption. They support the IEEE 802.15.4-2006 2.4‑GHz PHY requirements. The ADF7242 also supports proprietary GFSK/FSK/GMSK/MSK modulation schemes in both packet and data streaming modes. The Skyworks SE2431L, designed for 2.4 GHz applications, provides ease of use and maximum flexibility, with fully matched 50 Ω input and output, integrated interstage matching, harmonic filter, and digital controls that are compatible with 1.6 V to 3.6 V CMOS levels.
Heterodyne radios, such as the ADF7021 family of transceivers, use a mixer to down convert received RF signals to an intermediate frequency (IF). The output of the mixer contains the wanted frequency component along with an unwanted component at the image frequency. Unwanted signals present at the image frequency can degrade receiver sensitivity, resulting in loss of signal on the wanted channel. In theory, transceivers employing an I/Q receive architecture can be configured to infinitely reject the image frequency, assuming that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a digital control register until the quadrature signals are optimally balanced, providing maximum image rejection. This 11-page Application Note provides information on the mechanism that generates the image frequency and describes how image calibration can be implemented on the ADF7021, ADF7021-N, and ADF7021-V.
Various applications require the generation of two or more sinusoidal or square wave signals with a known phase relationship between them. The AD9915 DDS IC is capable of providing such signals. This 6-page Application Note offers detailed instructions on how to synchronize two or more of these devices and considers possible sources of phase error.
This true rms responding power detector uses a variable gain amplifier (VGA) and a power detector to provide a 95-dB wide detection range, making it useful for accurate measurement of signals with diverse or varying crest factors, such as those found in GSM/EDGE, CDMA, WCDMA, TD-SCDMA, and LTE receivers and transmitters. The 65-dB detection range of the ADL5902 rms detector is extended to 95 dB by the addition of the AD8368 linear-in-dB VGA.
This flexible, frequency agile, direct conversion IF-to-baseband receiver features a fixed 5-dB conversion gain to reduce the cascaded noise figure. Variable baseband gain adjusts the signal level, and a programmable low-pass filter eliminates out-of-channel blockers and noise. The filter bandwidth can be dynamically adjusted as the input signal bandwidth changes, ensuring full use of the available dynamic range of the driven ADC. The core circuit is an integrated I/Q demodulator with fractional-N PLL and VCO. With a single variable reference frequency, the PLL/VCO can provide a local oscillator (LO) between 750 MHz and 1150 MHz.
This broadband direct-conversion transmitter (analog baseband in, RF out) supports RF frequencies from 30 MHz to 2.2 GHz using a phase-locked loop (PLL) with an on-chip broadband voltage-controlled oscillator (VCO). Unlike modulators that use a divide-by-1 local oscillator (LO) stage, harmonic filtering of the LO is not required as long as the LO inputs to the modulator are driven differentially. The ADF4351 provides differential RF outputs and is, therefore, an excellent match. This PLL-to-modulator interface is useful for all I/Q modulators and I/Q demodulators that contain a 2XLO-based phase splitter.
This PLL circuit uses a 13-GHz fractional-N synthesizer, wideband active loop filter, and VCO, to achieve phase settling time of less than 5 μs to within 5° for a 200-MHz frequency jump. The performance is achieved using an active loop filter with 2.4-MHz bandwidth. This wideband loop filter is enabled by the 110-MHz maximum frequency of the ADF4159’s phase-frequency detector (PFD); and the 145-MHz gain-bandwidth product of the AD8065 op amp. The AD8065 can operate on a 24 V supply voltage, allowing control of most wideband VCOs having tuning voltages from 0 V to 18 V.
This high-performance phase locked loop (PLL) uses high-speed clock buffers and low-noise LDOs to maintain low phase noise even at low reference and RF frequencies. For example, the ADF4106 PLL specifies a 20-MHz minimum reference frequency and a 500-MHz minimum RF input frequency. This frequency range can be lowered to a 10-MHz reference frequency and a 100-MHz RF input frequency using additional clock buffers.
This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). It supports RF frequencies from 500 MHz to 4.4 GHz using a phase-locked loop (PLL) with a broadband, integrated voltage-controlled oscillator (VCO). Harmonic filtering of the local oscillator (LO) from the PLL ensures excellent quadrature accuracy, sideband suppression, and low EVM. Low noise, low dropout regulators (LDOs) ensure that the power management scheme has no adverse impact on phase noise and EVM. This combination of components represents industry leading direct conversion transmitter performance over a frequency range of 500 MHz to 4.4 GHz.
Whether an IQ modulator is used in a direct conversion application or as an upconverter to a first intermediate frequency (IF), some gain is generally applied directly after the IQ modulator. This circuit note describes how to choose an appropriate driver amplifier to provide the first stage of gain at the output of an IQ modulator. This circuit uses the ADL5375 IQ modulator and the ADL5320 driver amplifier, which are well matched from a system performance level. Because these devices are well matched in terms of their dynamic ranges, a simple direct connection between the IQ modulator and the RF driver amplifier is recommended without any need for attenuation between the devices.
This band-pass receiver front-end is based on the ADL5565 ultralow-noise differential amplifier driver and the AD9642 14-bit, 250-MSPS analog-to-digital converter (ADC). The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB. The overall circuit has a bandwidth of 18 MHz with a pass-band flatness of 3 dB. With a 127-MHz analog input, it features 71.7-dBFS signal-to-noise ratio (SNR) and 92-dBc spurious-free dynamic range (SFDR). The sampling frequency is 205 MSPS, thereby positioning the IF input signal in the second Nyquist zone between 102.5 MHz and 205 MHz.
This circuit provides a 16-bit, 250-MSPS, narrow-band, high-IF receiver front-end with an optimum interface between the ADL5565 differential amplifier with high input bandwidth, low distortion, and high output linearity and the AD9467 buffered-input 16-bit, 250-MSPS ADC with 75.5-dBFS SNR and 98‑dBFS. The systematic procedure for designing the interface circuit and antialiasing filter described here maintains high performance and ensures minimal signal loss. A resonant approach is used to design a maximally flat Butterworth fourth-order band-pass filter with 200-MHz center frequency.
This circuit is a 65-MHz bandwidth receiver front
end based on the
ADL5565 ultrahigh dynamic range differential amplifier driver and the
Precision Analog Microcontroller includes 14-bit analog I/O, MIDO interface, ARM Cortex-M3
ADuCM320 combines high-performance analog and digital peripherals, an
80-MHz ARM Cortex-M3 processor, and flash memory. The 14-bit, 1-MSPS ADC
accepts up to 16 single-ended or differential inputs, and can measure the
voltage at the IDAC outputs, the chip temperature, and the supply voltages;
a selection of channels can be measured in sequence without software
involvement. Up to eight VDACs provide output ranges of 0 to 2.5 V or 0 to
AVDD, and retain their output voltages during a
watchdog or software reset. Four IDACs provide output currents between 0 mA
and 150 mA. A low-drift band gap reference and a voltage comparator complete
the analog input peripheral set. The low-power ARM Cortex-M3 processor and
Isolated 16-bit Sigma-Delta Modulator
The AD7403 high-performance, second-order, Σ-Δ modulator converts an analog input into a high-speed, single-bit data stream, with on-chip digital isolation based on iCoupler technology. Operating from a 5-V supply, it accepts a ±250 mV (±320 mV full-scale) differential input signal, making it ideally suited to monitor shunt voltages in high-voltage applications that require galvanic isolation. The analog input is continuously sampled and converted to a bit stream at up to 20 MHz. The original signal can be reconstructed with a digital filter to achieve 88-dB signal-to-noise ratio (SNR) at 78.1 kSPS. The serial interface, which operates at 3 V or 5 V, provides 5-kV rms isolation and 25-kV/µs common-mode transient immunity. Available in a 16-lead SOIC package, the AD7403 is specified from –40°C to +125°C and priced at $3.35 in 1000s.
12-bit, 2.0-GSPS Pipelined ADC
The AD9625 sampling analog-to-digital converter achieves 12-bit performance at conversion rates of up to 2.0 GSPS. Designed for sampling wide bandwidth analog signals up through the 2nd Nyquist zone, its combination of wide input bandwidth, high sampling rate, and excellent linearity is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and electronic countermeasures (ECM). The JESD204B-based high-speed serialized outputs are configurable in a variety of one-, two-, four-, six-, or eight-lane arrangements. Operating on a 1.3-V and 2.5-V supplies, the AD9625 dissipates 3.5 W. Available in a 196-ball BG_ED package, it is specified from –40°C to +85°C and priced at $625.00 in 1000s.
Mixed-Signal Front-End (MxFE®)
The AD9993 mixed-signal front-end integrates four 14-bit ADCs and two 14-bit DACs. The high-speed DACs and multistage pipelined ADCs are designed to be used in wide bandwidth communication systems. The datapaths include FIFO buffers to absorb phase differences between LVDS lane clocks and the data converter sampling clocks. The devices is programmable via the SPI-compatible interface. Operating on 1.8-V and 3.3-V supplies, the AD9993 dissipates 1.5 W with a single-tone input and single-tone output and 33 mW in power-down mode. Available in a 196-ball CSP-BGA package, it is specified from –40°C to +85°C and priced at $148.70 in 1000s.
Integer-N/Fractional-N PLL Synthesizer
The ADF4155 implements fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter, VCO, and reference frequency up to 8 GHz. The high-resolution programmable modulus allows synthesis of exact frequencies. The VCO frequency can be divided by 1, 2, 4, 8, 16, 32, or 64 to generate RF output frequencies as low as 7.8125 MHz. All on-chip registers are controlled via a simple 3-wire interface. Operating on a 3.3-V supply, the ADF4155 draws 105 mA with the RF output enabled, 38 mA with the RF output disabled, 500 µA in software power-down mode, and 10 µA in hardware power-down mode. Available in a 24-lead LFCSP package, it is specified from –40°C to +85°C and priced at $5.02 in 1000s.
3-GHz Variable-Gain LNA includes 500-mW driver amplifier
The ADL5246 high-performance, low-noise variable-gain amplifier (VGA) is optimized for multistandard base station receivers and point-to-point receive (Rx) and transmit (Tx) applications. It consists of a low-noise amplifier, a high-linearity VGA, and a 500-mW output stage. The variable attenuator networks are optimized to provide high linearity over the 45-dB gain-control range. Gain is set using a 0-V to 3.3-V control voltage. The output stage is an externally tuned 500-mW driver amplifier that can be optimized anywhere in the 0.6-GHz to 3-GHz range, with a 200-MHz average tuning bandwidth. An external filter can be used between the VGA and the driver amplifier. The ADL5246 can be biased between 3.3 V and 5 V to trade-off between performance and power consumption, drawing 270 mA at 5 V and 141 mA at 3.3 V. Available in a 32-lead LFCSP package, it is specified from –40°C to +105°C and priced at $7.50 in 1000s.
Continuous-rate 8.5-Mbps to 11.3-Gbps Clock and Data Recovery IC with integrated limiting amp and equalizer
The ADN2917 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 8.5 Mbps to 11.3 Gbps, automatically locking to all data rates without an external reference clock. Its jitter performance exceeds all SONET/SDH requirements, including jitter transfer, jitter generation, and jitter tolerance. It provides manual or automatic slice adjust and manual sample phase adjusts; and users can select a limiting amplifier, adaptive or manually adjustable equalizer, or bypass at the input. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a programmable threshold. Hysteresis prevents chatter at the LOS output. The input signal strength can be read through the I2C registers. The device supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. Operating on 1.2-V, 1.8-V, and 3.3-V supplies, the ADN2917 dissipates 446.6 mW at 8.5 Gbps. Available in a 24-lead LFCSP package, it is specified from –40°C to +85°C and priced at $19.95 in 1000s.
Wideband Quadrature Modulator includes fractional-N PLL and four VCOs
The ADRF6720 wideband quadrature modulator with integrated synthesizer is ideally suited for 3G and 4G communication systems. Comprising a high-linearity broadband modulator, fractional-N phase-locked loop, and four low-phase-noise multicore VCOs, it offers digital programmability for carrier feedthrough optimization, sideband suppression, HD3/IP3 optimization, and high-side or low-side LO injection. The local oscillator (LO) can be generated externally, or internally via the on-chip integer-N and fractional-N-synthesizers. The multicore VCOs enable LO coverage from 356.25 MHz to 2855 MHz. Quadrature signals are generated with a divide-by-2 phase splitter or with a polyphase filter. Operating on a 3.3 V supply, the ADRF6720 draws 425 mA with the modulator enabled, 228 mA with the modulator disabled, and 14.5 mA in power-down mode. Available in a 40-lead LFCSP package, it is specified from –40°C to +85°C and priced at $7.95 in 1000s.
4-input, 8-output, Adaptive Clock Translator for multiservice line cards
AD9554 low-loop-bandwidth clock translator
provides jitter cleanup and synchronization for many systems, including
synchronous optical networks (SONET/SDH). It generates an output clock
synchronized to up to four external input references. The digital PLL (DPLL)
reduces input time jitter and phase noise associated with the external
references. The digitally controlled loop and holdover circuitry continues
to generate a low-jitter output clock even when all reference inputs have
failed. Eight differential clock outputs at frequencies from 430 kHz to 941
MHz are individually configurable for HCSL-, LVDS-, or LVPECL compatibility.
The devices support GR-1244 Stratum 3 stability in holdover mode, Telcordia
GR‑253 jitter specifications in up to OC-192 systems, and
Rob Reeder, GSPS Converter Wideband Front-End Design, DigiKey, 2014-05-28
Ian Beavers, Understanding Spurious-Free Dynamic Range In Wideband GSPS ADCs, Electronic Design, 2014-05-12
Qui Luu and Benjamin Sam, Differential Drive Optimizes Active Mixers, Microwaves&RF, 2014-04-11
Tom Gratzek, Product How-to: Sophisticated tools accelerate SDR exploration, EDN, 2014-04-08
Jarrett Liner, Understanding and designing wideband output networks for high speed D/A converters, EDN, 2014-03-19
Rob Reeder, Design Wideband Front Ends for GSPS Converters, Electronic Design, 2014-01-24
Kyle Slightom, Dual-Loop Clock Generator Cleans Jitter, Provides Multiple High-Frequency Outputs, Analog Dialogue, 2014-01-06
Duncan Bosworth, Multiband Analog Front End Brings One-Chip Radio Closer to Reality, Microwave Engineering Europe, 2013-12-02
Duncan Bosworth, Multiband Analogue Front End Brings One-Chip Radio Closer to Reality, EDN Europe, 2013-11-29
Jonathan Harris, Interleaving Spurs: Let’s Look at the Math, Planet Analog, 2013-09-17
Ray Sun, How to Design and Debug a Phase-Locked Loop (PLL) Circuit, Analog Dialogue, 2013-09-04
Jonathan Harris, Interleaving Spurs: Bandwidth Mismatches, Planet Analog, 2013-08-29
Yi Zhang and Assaf Toledano, High-Speed DACs Fuel Multiband Transmitters, Microwaves & RF, 2013-08-22
Developing Multiple-Input Multiple-Output (MIMO) Systems with the AD9361 - As software defined radio (SDR) and multiple-input multiple-output (MIMO) become more prevalent, there is a need for more channel diversity. This webcast will detail how to use multiple AD9361 RF agile transceivers to create an N×N MIMO system, as well as explore the available tradeoffs in the design. The AD9361 is a fully integrated 2×2 MIMO transceiver. Its programmability and wideband capability make it ideal for a broad range of transceiver applications.
Digital Filter Design for Integrated RF Transceivers - This webcast introduces how MATLAB from MathWorks can be used for complicated filter design in wireless SDR systems and components. We will create a model of the Analog Devices AD9361 and AD9364 RF transceivers, as integrated on the AD-FMCOMMS2-EBZ and AD-FMCOMMS4-EBZ SDR development platforms. We will use that model to design a filter for the internal FIR filters using the generated coefficients in an example system design.
Integrated Software-Defined Radio on Zynq®-7000 All Programmable SoC -- This course introduces wireless communication system design on the new Avnet Zynq®-7000 All Programmable SoC/AD9361 Software-Defined Radio Evaluation Kit featuring Analog Devices AD9361 single-chip RF agile transceiver. An IEEE 802.11 receiver example will demonstrate system-level simulation using MATLAB® and Simulink® modeling and code generation tools from MathWorks. Using the Xilinx Vivado® Design Suite, the system will be implemented for production showing the receiver detecting 802.11 beacon frames in a stand-alone system running UBUNTU desktop Linux on Xilinx Zynq AP SoC. Presentations will alternate with instructor-led demos to illustrate coding techniques within MathWorks and Xilinx development tools for high-speed digital signal processing.
Solving the Elusive Baseband to Antenna Problem using RFDAC Technology - This webinar will explore RF transmitter architectures, concentrating on the direct-to-RF architecture enabled by RFDAC technology. Aspects of the direct-to-RF transmitter system design will be explored including gain, signal bandwidth, digital signal processing requirements, frequency planning, thermal noise, clock synthesis + phase noise, harmonics, sampling images, pre-distortion techniques, and deterministic latency.
The Evolving Architecture of Military Communication Systems -- This webcast explores the different bands of Military Communications, and the advantages and disadvantages of each. We talk briefly about the shift toward software defined radios (SDR) and what that means for today’s system designers. We talk about traditional Tx/Rx signal chains for these radios, where they are heading in the future, and the key analog and mixed-signal technology that is driving these changes.
Fundamentals of Data Conversion in Receivers - This webinar examines a contemporary receive signal chain and takes a close look at selecting suitable data converters, their key specifications, and the tradeoffs that must be made.
Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS) – This concludes our two-part series on frequency synthesis with an introduction to direct digital synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
Fundamentals of Frequency Synthesis, Part 1: Phase Locked Loops – The first of a two-part series on frequency synthesis, with an introduction to phase locked loops (PLLs). This webcast looks at the need for frequency generation; techniques from the past, present, and future; how to assess the performance of a frequency synthesizer; and real world applications. Particular attention will be focused on phase locked loops as frequency synthesizers.
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