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This 7-page Application Note describes the Reed-Solomon firmware module, which contains both forward error correction and advanced encryption standard (AES) encryption, for the ADF7023 transceiver. Reed-Solomon encoding appends check symbols to the transmitted data. When received, these symbols detect the presence of errors and correct them in the received data. The firmware module is flexible, allowing the user to select values that enable correction of up to five error bytes within a packet. Encoded packets are resilient to burst and random errors; their coding gain improves link margin.
This 11-page Application Note describes the radio performance of the ADF7021-N transceiver when configured for operation according to the wireless meter-bus (WM-Bus) standard, focusing on key receiver parameters applicable to the 2.4 kbps and 4.8 kbps modes of operation. These parameters are packet error rate (PER) over power, sensitivity over carrier frequency error, blocking, and adjacent channel selectivity.
Heterodyne radios, such as the ADF7023 family of transceivers, use a mixer to downconvert received radio frequency (RF) signals to an intermediate frequency (IF). Interfering signals, called interferers, that lay on the image frequency are also mixed down to the wanted frequency. This desensitizes the receiver, resulting in blocking on the wanted channel. In theory, an ideal transceiver, which employs an IQ receive architecture, can be configured to eliminate the image frequency mixing onto the wanted channel. This theory assumes that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a firmware download module, until the quadrature signals are optimally balanced, providing maximum image rejection. This 6-page Application Note describes the fully autonomous image rejection (IR) calibration firmware download module for the ADF7023 transceiver IC. With minimum user input, this firmware optimizes the image rejection with a default configuration completely autonomously.
This 4-page Application Note provides information on the built-in packet error rate (PER) test mode on the ADF7023 and ADF7023-J. This mode helps the user to set up a communication link and test its quality. Up to 65,535 packets can be transmitted with a programmable delay between packets. The packet stored in packet RAM is transmitted each time. If the cyclic redundancy check (CRC) is correct, the receiver determines it has correctly received a packet.
When the ADF7023 receives a packet in packet mode, it stores the data in a linear sequence in the packet RAM. Prior to transmission, the data to be transmitted is written to the packet RAM in a linear sequence, as described in the ADF7023 data sheet. The ADF7023 packet RAM is 240 bytes long. If the packet length is greater than 240 bytes, additional measures are required. This 4-page Application Note describes a method for handling longer packet lengths on the ADF7023, up to a maximum length of 65,535 bytes, via a rolling buffer mechanism. This method reuses and renames several registers of the ADF7023.
This 11-page Application Note describes a reference design using the ADF7241/ADF7242 highly integrated, low power, high performance transceiver and the SE2431L fully integrated RF front-end. The ADF7241 and ADF7242, which operate in the global 2.4-GHz ISM band, provides flexibility, robustness, ease of use, and low current consumption. They support the IEEE 802.15.4-2006 2.4‑GHz PHY requirements. The ADF7242 also supports proprietary GFSK/FSK/GMSK/MSK modulation schemes in both packet and data streaming modes. The Skyworks SE2431L, designed for 2.4 GHz applications, provides ease of use and maximum flexibility, with fully matched 50 Ω input and output, integrated interstage matching, harmonic filter, and digital controls that are compatible with 1.6 V to 3.6 V CMOS levels.
Heterodyne radios, such as the ADF7021 family of transceivers, use a mixer to down convert received RF signals to an intermediate frequency (IF). The output of the mixer contains the wanted frequency component along with an unwanted component at the image frequency. Unwanted signals present at the image frequency can degrade receiver sensitivity, resulting in loss of signal on the wanted channel. In theory, transceivers employing an I/Q receive architecture can be configured to infinitely reject the image frequency, assuming that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a digital control register until the quadrature signals are optimally balanced, providing maximum image rejection. This 11-page Application Note provides information on the mechanism that generates the image frequency and describes how image calibration can be implemented on the ADF7021, ADF7021-N, and ADF7021-V.
Various applications require the generation of two or more sinusoidal or square wave signals with a known phase relationship between them. The AD9915 DDS IC is capable of providing such signals. This 6-page Application Note offers detailed instructions on how to synchronize two or more of these devices and considers possible sources of phase error.
This circuit provides upconversion of I/Q modulated data and automatic power control of the RF/IF carrier level. The output power is set by a 12-bit digital-to-analog converter (DAC) and can be precisely set over a linear-in-dB range of up to 30 dB. Stability over temperature is typically ±0.2 dB from −40°C to +85°C. The circuit operates from 50 MHz to 2.2 GHz.
This circuit combines the ADL5382 and AD9262 to provide an RF-to-bits solution with optimized performance, low cost, and minimal board space. This two-chip combination uses a single frequency translation step to convert the RF channel directly to the baseband without intermediate frequency translations. The frequency translation is accomplished by the ADL5382 broadband quadrature I/Q demodulator, which covers the RF input frequency range from 700 MHz to 2.7 GHz. The ADL5382 is followed by the AD9262 16-bit dual continuous time sigma-delta (Σ-Δ) analog-to-digital converter.
This circuit uses the ADL5534 IF amplifier to provide a dual IF gain block for the AD9640 14-bit, 150 MSPS dual ADC. The ADL5534 high linearity, dual amplifier with fixed 20 dB gain can be adapted for use as a driver for a high performance IF sampling ADC. The ADL5534 provides a simple approach to interfacing the RFIN signal level of 200 mV p-p to the 2 V p-p full scale of the high speed ADC. The low noise (2.5 dB NF at 70 MHz) and low distortion (IP3 of 40 dBm at 70 MHz) of the ADL5534 ensure that the ADC performance is not compromised.
This true rms responding power detector uses a variable gain amplifier (VGA) and a power detector to provide a 95-dB wide detection range, making it useful for accurate measurement of signals with diverse or varying crest factors, such as those found in GSM/EDGE, CDMA, WCDMA, TD-SCDMA, and LTE receivers and transmitters. The 65-dB detection range of the ADL5902 rms detector is extended to 95 dB by the addition of the AD8368 linear-in-dB VGA.
This flexible, frequency agile, direct conversion IF-to-baseband receiver features a fixed 5-dB conversion gain to reduce the cascaded noise figure. Variable baseband gain adjusts the signal level, and a programmable low-pass filter eliminates out-of-channel blockers and noise. The filter bandwidth can be dynamically adjusted as the input signal bandwidth changes, ensuring full use of the available dynamic range of the driven ADC. The core circuit is an integrated I/Q demodulator with fractional-N PLL and VCO. With a single variable reference frequency, the PLL/VCO can provide a local oscillator (LO) between 750 MHz and 1150 MHz.
This broadband direct-conversion transmitter (analog baseband in, RF out) supports RF frequencies from 30 MHz to 2.2 GHz using a phase-locked loop (PLL) with an on-chip broadband voltage-controlled oscillator (VCO). Unlike modulators that use a divide-by-1 local oscillator (LO) stage, harmonic filtering of the LO is not required as long as the LO inputs to the modulator are driven differentially. The ADF4351 provides differential RF outputs and is, therefore, an excellent match. This PLL-to-modulator interface is useful for all I/Q modulators and I/Q demodulators that contain a 2XLO-based phase splitter.
This PLL circuit uses a 13-GHz fractional-N synthesizer, wideband active loop filter, and VCO, to achieve phase settling time of less than 5 μs to within 5° for a 200-MHz frequency jump. The performance is achieved using an active loop filter with 2.4-MHz bandwidth. This wideband loop filter is enabled by the 110-MHz maximum frequency of the ADF4159’s phase-frequency detector (PFD); and the 145-MHz gain-bandwidth product of the AD8065 op amp. The AD8065 can operate on a 24 V supply voltage, allowing control of most wideband VCOs having tuning voltages from 0 V to 18 V.
This high-performance phase locked loop (PLL) uses high-speed clock buffers and low-noise LDOs to maintain low phase noise even at low reference and RF frequencies. For example, the ADF4106 PLL specifies a 20-MHz minimum reference frequency and a 500-MHz minimum RF input frequency. This frequency range can be lowered to a 10-MHz reference frequency and a 100-MHz RF input frequency using additional clock buffers.
This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). It supports RF frequencies from 500 MHz to 4.4 GHz using a phase-locked loop (PLL) with a broadband, integrated voltage-controlled oscillator (VCO). Harmonic filtering of the local oscillator (LO) from the PLL ensures excellent quadrature accuracy, sideband suppression, and low EVM. Low noise, low dropout regulators (LDOs) ensure that the power management scheme has no adverse impact on phase noise and EVM. This combination of components represents industry leading direct conversion transmitter performance over a frequency range of 500 MHz to 4.4 GHz.
Whether an IQ modulator is used in a direct conversion application or as an upconverter to a first intermediate frequency (IF), some gain is generally applied directly after the IQ modulator. This circuit note describes how to choose an appropriate driver amplifier to provide the first stage of gain at the output of an IQ modulator. This circuit uses the ADL5375 IQ modulator and the ADL5320 driver amplifier, which are well matched from a system performance level. Because these devices are well matched in terms of their dynamic ranges, a simple direct connection between the IQ modulator and the RF driver amplifier is recommended without any need for attenuation between the devices.
This band-pass receiver front-end is based on the ADL5565 ultralow-noise differential amplifier driver and the AD9642 14-bit, 250-MSPS analog-to-digital converter (ADC). The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB. The overall circuit has a bandwidth of 18 MHz with a pass-band flatness of 3 dB. With a 127-MHz analog input, it features 71.7-dBFS signal-to-noise ratio (SNR) and 92-dBc spurious-free dynamic range (SFDR). The sampling frequency is 205 MSPS, thereby positioning the IF input signal in the second Nyquist zone between 102.5 MHz and 205 MHz.
This circuit provides a 16-bit, 250-MSPS, narrow-band, high-IF receiver front-end with an optimum interface between the ADL5565 differential amplifier with high input bandwidth, low distortion, and high output linearity and the AD9467 buffered-input 16-bit, 250-MSPS ADC with 75.5-dBFS SNR and 98‑dBFS. The systematic procedure for designing the interface circuit and antialiasing filter described here maintains high performance and ensures minimal signal loss. A resonant approach is used to design a maximally flat Butterworth fourth-order band-pass filter with 200-MHz center frequency.
This circuit is a 65-MHz bandwidth receiver front
end based on the
ADL5565 ultrahigh dynamic range differential amplifier driver and the
RF Agile Transceiver
The AD9364 high-performance, highly integrated, low-power RF agile transceiver offers programmability and wideband capability that make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. Operating in the 70 MHz to 6.0 GHz range, with channel bandwidths from 200 kHz to 56 MHz, the transceiver supports most licensed and unlicensed bands. Available in a 10-mm × 10-mm, 144-ball CSP_BGA package, the AD9364 is priced at $130.00 in 1000s.
Continuous-rate 6.5-Mbps to 8.5-Gbps Clock and Data Recovery IC
The ADN2913 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 6.5 Mbps to 8.5 Gbps, automatically locking to all data rates without an external reference clock. Its jitter performance exceeds all SONET/SDH requirements, including jitter transfer, jitter generation, and jitter tolerance. It provides manual or automatic slice adjust and manual sample phase adjusts; and users can select a limiting amplifier, adaptive or manually adjustable equalizer, or bypass at the input. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a programmable threshold. Hysteresis prevents chatter at the LOS output. The input signal strength can be read through the I2C registers. The device supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. Operating on 1.2-V, 1.8-V, and 3.3-V supplies, the ADN2913 dissipates 388 mW at 4.25 Gbps. Available in a 24-lead LFCSP package, it is specified from –40°C to +85°C and priced at $29.95 in 1000s.
Quad 16-bit, 125-MSPS Pipelined ADC provides JESD204B outputs
AD9656 quad, 16-bit, 125-MSPS pipelined
analog-to-digital converter includes four high-speed, low-power ADCs,
versatile serial and JESD204B interfaces, and a buffered voltage reference.
Sampling at up to 125 MSPS, it achieves
Dual 16-bit, 1600-MSPS TxDAC+ Digital-to-Analog Converter
AD9142A dual 16-bit, 1600-MSPS TxDAC+®
digital-to-analog converter enables multicarrier signal generation at
frequencies up to Nyquist. Optimized for direct-conversion transmit
applications, it includes complex digital modulation; input signal power
detection; and gain, phase, and offset compensation. The 2×/4×/8×
interpolator/complex modulator enables carrier placement anywhere within the
DAC bandwidth. The DAC outputs interface seamlessly with quadrature
modulators in the ADL537x
695-MHz to 2700-MHz Quadrature Demodulator includes fractional-N PLL, VCO
The ADRF6820 highly integrated demodulator and synthesizer is ideally suited for next-generation communication systems. The feature rich device consists of a high-linearity broadband I/Q demodulator, a fractional-N phase-locked loop (PLL), a low phase noise multicore voltage-controlled oscillator (VCO, a 2:1 RF switch, a tunable RF balun, a programmable RF attenuator, and two low dropout (LDO) regulators. The high isolation 2:1 RF switch and tunable RF balun support two single-ended, 50-Ω terminated RF inputs. The programmable attenuator offers a 0-dB to 15-dB attenuation range with a 1‑dB step size to ensure an optimal differential RF input level. The differential local oscillator (LO) input signal can be generated externally via a high-frequency, low-phase-noise LO signal or internally via the fractional-N synthesizer, which enables continuous LO coverage from 356.25 MHz to 2850 MHz. The PLL reference input supports a wide frequency range; divide or multiply blocks can increase or decrease the reference frequency to the desired value before it is passed to the phase frequency detector (PFD). When selected, the output of the fractional-N synthesizer is applied to a divide-by-2 quadrature phase splitter. From the external LO path, a 1× LO signal can be applied to the built-in polyphase filter, or a 2× LO signal can be used with the divide-by-2 quadrature phase splitter to generate the quadrature LO inputs to the mixers. Operating on 3.3-V and 5-V supplies, the ADRF6820 dissipates 1.4 W with internal PLL and VCO and 1.1 W with an external filter. Available in a 40-lead LFCSP package, it is specified from –40°C to +85°C and priced at $12.98 in 1000s.
Rob Reeder, Design Wideband Front Ends for GSPS Converters, Electronic Design, 2014-01-24
Kyle Slightom, Dual-Loop Clock Generator Cleans Jitter, Provides Multiple High-Frequency Outputs, Analog Dialogue, 2014-01-06
Duncan Bosworth, Multiband Analog Front End Brings One-Chip Radio Closer to Reality, Microwave Engineering Europe, 2013-12-02
Duncan Bosworth, Multiband Analogue Front End Brings One-Chip Radio Closer to Reality, EDN Europe, 2013-11-29
Jonathan Harris, Interleaving Spurs: Let’s Look at the Math, Planet Analog, 2013-09-17
Ray Sun, How to Design and Debug a Phase-Locked Loop (PLL) Circuit, Analog Dialogue, 2013-09-04
Jonathan Harris, Interleaving Spurs: Bandwidth Mismatches, Planet Analog, 2013-08-29
Yi Zhang and Assaf Toledano, High-Speed DACs Fuel Multiband Transmitters, Microwaves & RF, 2013-08-22
Ashraf Elghamrawi, High Performance Driver Amplifiers, Microwave Journal, 2013-02-14
T.V.B. Subrahmanyam and Mohammed Chalil,
The Successful Implementation of High-Performance Digital Radio, Analog
Daniel Fague and Sara Nadeau, RF DACs simplify power and space in downstream cable transmitter systems, EDN, 2012-12-15
Robert Brennan, High-Performance 13 GHz PLL Synthesizer, Microwave Journal, 2012-11-01
Eamon Nash, Problem Solving To Make RF And Mixed Signal Components Speak The Same Language, RF Globalnet, 2012-10-03
Gil Engel, Dan Fague and Assaf Toledano, RF Digital-to-Analog Converters Enable Direct Synthesis of Communications Signals, IEEE Communications, 2012-10-01
Digital Filter Design for Integrated RF Transceivers - This webcast introduces how MATLAB from MathWorks can be used for complicated filter design in wireless SDR systems and components. We will create a model of the Analog Devices AD9361 and AD9364 RF transceivers, as integrated on the AD-FMCOMMS2-EBZ and AD-FMCOMMS4-EBZ SDR development platforms. We will use that model to design a filter for the internal FIR filters using the generated coefficients in an example system design.
Integrated Software-Defined Radio on Zynq®-7000 All Programmable SoC -- This course introduces wireless communication system design on the new Avnet Zynq®-7000 All Programmable SoC/AD9361 Software-Defined Radio Evaluation Kit featuring Analog Devices AD9361 single-chip RF agile transceiver. An IEEE 802.11 receiver example will demonstrate system-level simulation using MATLAB® and Simulink® modeling and code generation tools from MathWorks. Using the Xilinx Vivado® Design Suite, the system will be implemented for production showing the receiver detecting 802.11 beacon frames in a stand-alone system running UBUNTU desktop Linux on Xilinx Zynq AP SoC. Presentations will alternate with instructor-led demos to illustrate coding techniques within MathWorks and Xilinx development tools for high-speed digital signal processing.
Solving the Elusive Baseband to Antenna Problem using RFDAC Technology - This webinar will explore RF transmitter architectures, concentrating on the direct-to-RF architecture enabled by RFDAC technology. Aspects of the direct-to-RF transmitter system design will be explored including gain, signal bandwidth, digital signal processing requirements, frequency planning, thermal noise, clock synthesis + phase noise, harmonics, sampling images, pre-distortion techniques, and deterministic latency.
The Evolving Architecture of Military Communication Systems -- This webcast explores the different bands of Military Communications, and the advantages and disadvantages of each. We talk briefly about the shift toward software defined radios (SDR) and what that means for today’s system designers. We talk about traditional Tx/Rx signal chains for these radios, where they are heading in the future, and the key analog and mixed-signal technology that is driving these changes.
Fundamentals of Data Conversion in Receivers - This webinar examines a contemporary receive signal chain and takes a close look at selecting suitable data converters, their key specifications, and the tradeoffs that must be made.
Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS) – This concludes our two-part series on frequency synthesis with an introduction to direct digital synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
Fundamentals of Frequency Synthesis, Part 1: Phase Locked Loops – The first of a two-part series on frequency synthesis, with an introduction to phase locked loops (PLLs). This webcast looks at the need for frequency generation; techniques from the past, present, and future; how to assess the performance of a frequency synthesizer; and real world applications. Particular attention will be focused on phase locked loops as frequency synthesizers.
Solutions for Fitting High Performance RF Signal Chains into Small Spaces - This webinar will present the current state of integration of RF IC technology, with a focus on the challenges that non-handset-based wireless equipment designers face as they strive for more functionality in smaller spaces, sometimes with the added headache of having to implement broadband transceivers that can be reused at multiple frequencies.
Fundamentals of the RF Transmission and Reception of Digital Signals - Digital Modulation is an important topic for RF designers because most modern day transceivers transmit and receive digitally modulated data. In this webcast, part of ADI's continuing FUNDAMENTALS OF DESIGN series we will introduce you to the challenges—and solutions—for digital modulation. This webcast is a great way for beginners to get introduced to this vital communications standard or for veteran RF designers learn what's new in the field.
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