Communications Infrastructure

Application Notes

AN-1182: Understanding and Optimizing the AFC Loop on the ADF7021 for Minimum Preamble

Remote transceivers within radio communication networks use their own independent clock sources, and are thus susceptible to frequency errors. When a transmitter initiates a communication link, the associated receiver must correct these errors during the preamble phase of the data packet to ensure correct demodulation. An effective design block that performs this correction is an automatic frequency control (AFC) loop. This 7‑page Application Note provides information on how AFC is implemented and optimized on the ADF7021, ADF7021-N, and ADF7021-V.

Bleed Current Improves Noise and Spurious Performance of PLL

AN-1154: Optimizing Phase Noise and Spur Performance of the ADF4157 and ADF4158 PLLs Using Constant Negative Bleed

The phase noise (PN) and integer boundary spur (IBS) performance of the ADF4157 and the ADF4158 fractional-N frequency synthesizers can be improved by activating a constant negative bleed current. The biggest improvement is achieved at frequencies close or equal to integer multiples of the phase-frequency-detector (PFD) frequency. This 5-page Application Note describes how to implement a bleed current and measure its effects.

Impedance-Matched Filter Balun Boosts Performance of RF Transceivers

AN-1151: Using a Johanson 2450BM14E0007 Impedance-Matched, Integrated Filter Balun with the ADF7241 and ADF7242

This 6-page Application Note describes the use and performance achieved by the Johanson Technology, Inc., 2450BM14E0007 impedance-matched (complex differential impedance value) filter balun with the ADF7241 or ADF7242 2.4-GHz RF transceivers. The filter balun effectively reduces the RF front-end component count and layout space. This balun is 100% RF tested by Johanson Technology. Additional Information provides insight into how harmonic emissions are attenuated and further details about the balun.

DDS Setup Avoids Spurious Outputs During Device Initialization

AN-1108: AD9832/AD9835 Programming Examples

This 4-page Application Note describes how to load a sinusoidal waveform on the output of the AD9832/AD9835 direct digital synthesizers, including setting up the power-on scenario and FSELECT control bit, and loading new data to the part while using the FSELECT control bit.

Sideband Suppression Decreases Error Vector Magnitude and Bit Error Rate

AN-1100: Wireless Transmitter IQ Balance and Sideband Suppression

Direct modulation of the output IQ signals from a digital-to-analog converter onto an RF carrier (direct conversion) eliminates the need for an intermediate IF stage and associated filtering, making direct complex modulation the architecture of choice for transmitters in cellular base stations, WiMAX, and wireless point-to-point applications. During the analog modulation process, gain and phase mismatches of IQ signals directly impact the sideband suppression, resulting in degraded error vector magnitude (EVM) and increased bit error rate (BER). This 8-page Application Note discusses major causes of nonideal sideband suppression, and design considerations for component selection and PCB design/layout.

Circuits from the Lab

Broadband Low Error Vector Magnitude (EVM) Direct Conversion Transmitter (CN0285)

This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). It supports RF frequencies from 500 MHz to 4.4 GHz using a phase-locked loop (PLL) with a broadband, integrated voltage-controlled oscillator (VCO). Harmonic filtering of the local oscillator (LO) from the PLL ensures excellent quadrature accuracy, sideband suppression, and low EVM. Low noise, low dropout regulators (LDOs) ensure that the power management scheme has no adverse impact on phase noise and EVM. This combination of components represents industry leading direct conversion transmitter performance over a frequency range of 500 MHz to 4.4 GHz.

Broadband, Low Error Vector Magnitude (EVM) Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0311)

This broadband direct-conversion transmitter (analog baseband in, RF out) supports RF frequencies from 30 MHz to 2.2 GHz using a phase-locked loop (PLL) with an on-chip broadband voltage-controlled oscillator (VCO). Unlike modulators that use a divide-by-1 local oscillator (LO) stage, harmonic filtering of the LO is not required as long as the LO inputs to the modulator are driven differentially. The ADF4351 provides differential RF outputs and is, therefore, an excellent match. This PLL-to-modulator interface is useful for all I/Q modulators and I/Q demodulators that contain a 2XLO-based phase splitter.

Providing Fixed Power Gain at the Output of an IQ Modulator (CN0283)

Whether an IQ modulator is used in a direct conversion application or as an upconverter to a first intermediate frequency (IF), some gain is generally applied directly after the IQ modulator. This circuit note describes how to choose an appropriate driver amplifier to provide the first stage of gain at the output of an IQ modulator. This circuit uses the ADL5375 IQ modulator and the ADL5320 driver amplifier, which are well matched from a system performance level. Because these devices are well matched in terms of their dynamic ranges, a simple direct connection between the IQ modulator and the RF driver amplifier is recommended without any need for attenuation between the devices.

High IF Sampling Receiver Front End with Band-Pass Filter (CN0279)

This band-pass receiver front-end is based on the ADL5565 ultralow-noise differential amplifier driver and the AD9642 14-bit, 250-MSPS analog-to-digital converter (ADC). The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB. The overall circuit has a bandwidth of 18 MHz with a pass-band flatness of 3 dB. With a 127-MHz analog input, it features 71.7-dBFS signal-to-noise ratio (SNR) and 92-dBc spurious-free dynamic range (SFDR). The sampling frequency is 205 MSPS, thereby positioning the IF input signal in the second Nyquist zone between 102.5 MHz and 205 MHz.

Resonant Approach to Designing a Band-Pass Filter for Narrow-Band, High IF, 16-Bit, 250 MSPS Receiver Front End (CN0268)

This circuit provides a 16-bit, 250-MSPS, narrow-band, high-IF receiver front-end with an optimum interface between the ADL5565 differential amplifier with high input bandwidth, low distortion, and high output linearity and the AD9467 buffered-input 16-bit, 250-MSPS ADC with 75.5-dBFS SNR and 98‑dBFS. The systematic procedure for designing the interface circuit and antialiasing filter described here maintains high performance and ensures minimal signal loss. A resonant approach is used to design a maximally flat Butterworth fourth-order band-pass filter with 200-MHz center frequency.

High Performance 65 MHz Bandwidth Quad IF Receiver with Antialiasing Filter and 184.32 MSPS Sampling Rate (CN0259)

This circuit is a 65-MHz bandwidth receiver front end based on the ADL5565 ultrahigh dynamic range differential amplifier driver and the 11-bit, 200-MSPS AD6657A quad IF receiver. The fourth-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and IF receiver. The total insertion loss due the filter network and other resistive components is only 2.0 dB. The overall circuit has 65-MHz bandwidth; the low-pass filter has 190-MHz –1-dB bandwidth and 210-MHz –3-dB bandwidth. The pass-band flatness is 1 dB. The circuit is optimized to process a 65-MHz bandwidth IF signal centered at 140 MHz with a sampling rate of 184.32 MSPS. Measured with a 140-MHz analog input across the 65-MHz band, the circuit features 70.1-dBFS SNR and 80.9-dBc SFDR.

An IQ Demodulator-Based IF-to-Baseband Receiver with IF and Baseband Variable Gain and Programmable Baseband Filtering (CN0248) 

This circuit implements a flexible, frequency agile IF-to-baseband receiver. Variable IF and baseband gains adjust the signal level. The ADRF6510 baseband ADC driver includes a programmable low-pass filter that eliminates out-of-channel blockers and noise. The filter bandwidth can be dynamically adjusted as the bandwidth of the input signal changes, ensuring that the available dynamic range of the ADC is fully used. The core of the circuit is an IQ demodulator. The 2×LO-based phase-splitting architecture of the ADL5387 allows for operation over a wide frequency range. Precise quadrature balance and low output dc offsets ensure minimal degradation of the error vector magnitude (EVM). This fully differential circuit provides compatible bias levels where dc coupling is required between stages.

Wideband LO PLL Synthesizer with Simple Interface to Quadrature Demodulators (CN0245)

This circuit demonstrates the ease of interfacing the ADF4350 wideband synthesizer with integrated VCO with the ADL5380 and ADL5387 wideband I/Q demodulators. In this circuit, the ADF4350 provides the high frequency, low phase noise local oscillator (LO) signal to the wideband I/Q demodulator. This circuit configuration offers quite a few benefits that make it an attractive solution in applications requiring quadrature mixing down to baseband or to an intermediate frequency.

High Dynamic Range RF Transmitter Signal Chain using Single External Frequency Reference for DAC Sample Clock and IQ Modulator LO Generation (CN0243)

The combination of the ADRF6702 IQ modulator and the AD9122 16-bit dual 1.2-GSPS TxDAC has the dynamic range necessary for a modern high-level QAM or OFDM based wireless transmitter, enabling both ZIF (zero IF/baseband) and CIF (complex IF up to 200 MHz to 300 MHz). The ADRF6702 includes an on-board fractional PLL for LO generation so that a low-frequency reference (typically less than 100 MHz) is all that is required to synthesize the IQ modulator LO. Using the PLL in the AD9516 clock generator allows a single reference to generate both the DAC sample clock and the PLL reference for the ADRF6702.

High Performance, High IF, 75 MHz Bandwidth, 14-Bit, 250 MSPS Receiver Front End with Band-Pass Antialiasing Filter (CN0242)

This circuit is a 75 MHz bandwidth receiver front end based on the ADL5202 wide dynamic range, high speed, digitally controlled variable gain amplifier (VGA) and the 14-bit, 250 MSPS AD9643 dual ADC. The fifth-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and the ADC. The total insertion loss due to the filter network and other resistive components is approximately 2.3 dB. The overall circuit with the band-pass filter has a 1 dB bandwidth of 75 MHz (from 145 MHz to 220 MHz) and a 3 dB bandwidth of 110 MHz (from 120 MHz to 230 MHz). The pass-band flatness is 1 dB. The circuit is optimized to process a 75 MHz bandwidth IF signal centered at 182.5 MHz (second Nyquist zone) with a sampling rate of 245.76 MSPS. The signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) measured with a 182.5 MHz analog input across the 75 MHz band are 68.4 dBFS and 80.7 dBc, respectively.

High Performance, 12-Bit, 500 MSPS Wideband Receiver with Antialiasing Filter (CN0238)

This circuit is a wideband receiver front-end based on the ADA4960-1 ultralow-noise differential amplifier driver and the AD9434 12-bit, 500-MSPS analog-to-digital converter. The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network, transformer, and other resistive components is only 1.2 dB. The overall circuit has a bandwidth of 290 MHz with a pass-band flatness of 1 dB. The SNR and SFDR measured with a 140 MHz analog input are 64.1 dBFS and 70.4 dBc, respectively.

Minimizing Spurious Outputs Using a Synthesizer with an Integrated VCO and an External PLL Circuit (CN0232)

This circuit uses the ADF4350 synthesizer with integrated VCO plus an ADF4153 or ADF4157 PLL to minimize spurious outputs by isolating the PLL synthesizer circuitry from the VCO circuit. Due to the close proximity of the PLL circuitry to the VCO, devices with integrated PLLs and VCOs often have feed through from the digital PLL circuitry to the VCO, leading to higher spurious levels. The ADF4350 fully integrated fractional-N PLL and VCO can generate frequencies from 137.5 MHz to 4400 MHz. In addition to improved spurious performance, using an external PLL can increase frequency resolution to 0.7 Hz.

New Product Briefs

May 2013

10-MHz to 10-GHz RMS Power Detector has 67-dB dynamic range

The ADL5906 TruPwr™ rms-responding power detector provides a 67-dB dynamic range over the 10-MHz to 10-GHz frequency range. Driven from a single-ended 50-Ω source, it does not require a balun or other external input tuning, making it versatile and easy to use to control transmitter power or indicate signal strength. It provides excellent temperature stability, significantly easing calibration routines. Accepting inputs with rms values from –65 dBm to +8 dBm with varying crest factors and bandwidths, it can handle GSM-EDGE, CDMA, W-CDMA, TD-SCDMA, WiMAX, and LTE signals. When used in measurement mode, the output is proportional to the log of the rms value of the input, with a scaling factor of 55 mV/dB. In controller mode, an applied voltage determines the power level. Operating on a single 4.75-V to 5.25-V supply, the ADL5906 consumes 68 mA at –60 dBm and 250 µA in power-down mode. A-/S-grades, specified from –40°C /–55°C to +105°C/+125°C, are available in 16‑lead LFCSP packages and priced at $5.59/$12.57 in 1000s.

March 2013

Low-power 14-bit, 180-MSPS Digital-to-Analog Converter and Waveform Generator

The AD9102 TxDAC^® digital-to-analog converter combines a high-performance DAC with on-chip pattern memory for complex waveform generation using a direct digital synthesizer (DDS). The DDS generates a 14-bit sine wave at up to 180 MHz for use as a master clock. A 24-bit tuning word enables 10.8-Hz frequency resolution; an SRAM can store waveforms, modulation patterns, and DDS tuning words; and a state machine programs the period and start delay within the period. Control and configuration data is loaded via an SPI-compatible interface. Operating on a single 1.8-V supply, the AD9102 dissipates 51 mW at 180 MSPS and 1.49 mW in power-down mode. Available in a 32‑lead LFCSP package, it is specified from –40°C to +85°C and priced at $12.35 in 1000s.

1.65-GHz Clock Fanout Buffer includes frequency dividers and phase shifters

The AD9508 clock buffer, designed for high-speed, low-jitter applications, accepts one single-ended or differential input clock and provides up to four differential LVDS/HSTL output clocks at up to 1.65 GHz or eight single-ended 1.8-V CMOS output clocks at up to 250 MHz. Each output can be divided by any integer up to 1024, and coarse phase adjustments can be made between the outputs. Pin strapping allows various configurations to be set at power up without the need for SPI or I²C programming. Operating with a 2.375-V to 3.465-V supply, the AD9508 draws 185 mA with HSTL outputs, 152 mA with LVDS outputs, 141 mA with CMOS outputs, and 6 mA in power-down mode. Specified from –40°C to +85°C, it is available in a 24-lead LFCSP package and priced at $4.25 in 1000s.

Low-cost Logarithmic Converter features 160-dB range

The ADL5303 logarithmic detector is optimized to measure low-frequency signal power in fiber optic systems. Providing 160-dB dynamic range (100 pA to 10 mA), it achieves 0.1-dB log conformance from 1 nA to 1 mA. The laser-trimmed log slope of 10 mV/dB (200 mV/decade) can be adjusted to fit the available span, and an on-chip reference allows the intercept to be repositioned. An adaptive biasing scheme reduces photodiode dark current at very low light levels. The bandwidth, which is proportional to the input current, increases from 2 kHz at 1 nA to a maximum of 10 MHz. Operating with a 3.0-V to 5.5-V supply, the ADL5303 draws 45 mA in normal mode and 60 µA when disabled. Specified from –40°C to +85°C, it is available in a 16-lead LFCSP package and priced at $4.47 in 1000s.

Technical Articles

Ashraf Elghamrawi, High Performance Driver Amplifiers, Microwave Journal, 2013-02-14

T.V.B. Subrahmanyam and Mohammed Chalil, The Successful Implementation of High-Performance Digital Radio, Analog Dialogue, 2013-01-02

Daniel Fague and Sara Nadeau, RF DACs simplify power and space in downstream cable transmitter systems, EDN, 2012-12-15

Robert Brennan, High-Performance 13 GHz PLL Synthesizer, Microwave Journal, 2012-11-01

Eamon Nash, Problem Solving To Make RF And Mixed Signal Components Speak The Same Language, RF Globalnet, 2012-10-03

Gil Engel, Dan Fague and Assaf Toledano, RF Digital-to-Analog Converters Enable Direct Synthesis of Communications Signals, IEEE Communications, 2012-10-01

Eamon Nash and Ashraf Elghamrawi, RF Component Integration – Saving Space in High Performance Applications, High Frequency Electronics, 2012-09-18

Ken Gentile and David Brandon, DDS Clocks To 3.5 GHz, Microwaves & RF, 2012-09-01

Ashraf Elghamrawi, Industry's First Half Watt Driver Amplifier, Technology Review, 2012-07-15

Eamon Nash, Can’t RF and Mixed Signal Components Just Get Along? Overcoming the Challenge of RF Level Planning that Incorporates Mixed Signal Components, Microwave Product Digest, 2012-07-01

Webinars and Tutorials

Solving the Elusive Baseband to Antenna Problem using RFDAC Technology - This webinar will explore RF transmitter architectures, concentrating on the direct-to-RF architecture enabled by RFDAC technology. Aspects of the direct-to-RF transmitter system design will be explored including gain, signal bandwidth, digital signal processing requirements, frequency planning, thermal noise, clock synthesis + phase noise, harmonics, sampling images, pre-distortion techniques, and deterministic latency.

The Evolving Architecture of Military Communication Systems -- This webcast explores the different bands of Military Communications, and the advantages and disadvantages of each. We talk briefly about the shift toward software defined radios (SDR) and what that means for today’s system designers. We talk about traditional Tx/Rx signal chains for these radios, where they are heading in the future, and the key analog and mixed-signal technology that is driving these changes.

Fundamentals of Data Conversion in Receivers - This webinar examines a contemporary receive signal chain and takes a close look at selecting suitable data converters, their key specifications, and the tradeoffs that must be made.

Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS) – This concludes our two-part series on frequency synthesis with an introduction to direct digital synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.

Fundamentals of Frequency Synthesis, Part 1: Phase Locked Loops – The first of a two-part series on frequency synthesis, with an introduction to phase locked loops (PLLs). This webcast looks at the need for frequency generation; techniques from the past, present, and future; how to assess the performance of a frequency synthesizer; and real world applications. Particular attention will be focused on phase locked loops as frequency synthesizers.

Solutions for Fitting High Performance RF Signal Chains into Small Spaces - This webinar will present the current state of integration of RF IC technology, with a focus on the challenges that non-handset-based wireless equipment designers face as they strive for more functionality in smaller spaces, sometimes with the added headache of having to implement broadband transceivers that can be reused at multiple frequencies.

Fundamentals of the RF Transmission and Reception of Digital Signals - Digital Modulation is an important topic for RF designers because most modern day transceivers transmit and receive digitally modulated data. In this webcast, part of ADI's continuing FUNDAMENTALS OF DESIGN series we will introduce you to the challenges—and solutions—for digital modulation. This webcast is a great way for beginners to get introduced to this vital communications standard or for veteran RF designers learn what's new in the field.

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