|Home Analog Devices Feedback Subscribe Archives 简体中文 日本語|
This 11-page Application Note describes a reference design using the ADF7241/ADF7242 highly integrated, low power, high performance transceiver and the SE2431L fully integrated RF front-end. The ADF7241 and ADF7242, which operate in the global 2.4-GHz ISM band, provides flexibility, robustness, ease of use, and low current consumption. They support the IEEE 802.15.4-2006 2.4‑GHz PHY requirements. The ADF7242 also supports proprietary GFSK/FSK/GMSK/MSK modulation schemes in both packet and data streaming modes. The Skyworks SE2431L, designed for 2.4 GHz applications, provides ease of use and maximum flexibility, with fully matched 50 Ω input and output, integrated interstage matching, harmonic filter, and digital controls that are compatible with 1.6 V to 3.6 V CMOS levels.
Heterodyne radios, such as the ADF7021 family of transceivers, use a mixer to down convert received RF signals to an intermediate frequency (IF). The output of the mixer contains the wanted frequency component along with an unwanted component at the image frequency. Unwanted signals present at the image frequency can degrade receiver sensitivity, resulting in loss of signal on the wanted channel. In theory, transceivers employing an I/Q receive architecture can be configured to infinitely reject the image frequency, assuming that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a digital control register until the quadrature signals are optimally balanced, providing maximum image rejection. This 11-page Application Note provides information on the mechanism that generates the image frequency and describes how image calibration can be implemented on the ADF7021, ADF7021-N, and ADF7021-V.
This circuit provides upconversion of I/Q modulated data and automatic power control of the RF/IF carrier level. The output power is set by a 12-bit digital-to-analog converter (DAC) and can be precisely set over a linear-in-dB range of up to 30 dB. Stability over temperature is typically ±0.2 dB from −40°C to +85°C. The circuit operates from 50 MHz to 2.2 GHz.
This circuit combines the ADL5382 and AD9262 to provide an RF-to-bits solution with optimized performance, low cost, and minimal board space. This two-chip combination uses a single frequency translation step to convert the RF channel directly to the baseband without intermediate frequency translations. The frequency translation is accomplished by the ADL5382 broadband quadrature I/Q demodulator, which covers the RF input frequency range from 700 MHz to 2.7 GHz. The ADL5382 is followed by the AD9262 16-bit dual continuous time sigma-delta (Σ-Δ) analog-to-digital converter.
This circuit uses the ADL5534 IF amplifier to provide a dual IF gain block for the AD9640 14-bit, 150 MSPS dual ADC. The ADL5534 high linearity, dual amplifier with fixed 20 dB gain can be adapted for use as a driver for a high performance IF sampling ADC. The ADL5534 provides a simple approach to interfacing the RFIN signal level of 200 mV p-p to the 2 V p-p full scale of the high speed ADC. The low noise (2.5 dB NF at 70 MHz) and low distortion (IP3 of 40 dBm at 70 MHz) of the ADL5534 ensure that the ADC performance is not compromised.
This circuit combines the AD9552 oscillator frequency upconverter and ADCLK854 LVDS/CMOS clock fanout buffer to create a flexible pin-programmable clock distribution solution. The AD9552 is equipped with an SPI port to program the device. The 900-MHz output frequency range is pin-programmable, with up to 64 standard output frequencies, allowing the AD9552 to function as a frequency programmable VCXO. The AD9552 is also equipped to use a crystal resonator at the input for additional flexibility.
This true rms responding power detector uses a variable gain amplifier (VGA) and a power detector to provide a 95-dB wide detection range, making it useful for accurate measurement of signals with diverse or varying crest factors, such as those found in GSM/EDGE, CDMA, WCDMA, TD-SCDMA, and LTE receivers and transmitters. The 65-dB detection range of the ADL5902 rms detector is extended to 95 dB by the addition of the AD8368 linear-in-dB VGA.
This flexible, frequency agile, direct conversion IF-to-baseband receiver features a fixed 5-dB conversion gain to reduce the cascaded noise figure. Variable baseband gain adjusts the signal level, and a programmable low-pass filter eliminates out-of-channel blockers and noise. The filter bandwidth can be dynamically adjusted as the input signal bandwidth changes, ensuring full use of the available dynamic range of the driven ADC. The core circuit is an integrated I/Q demodulator with fractional-N PLL and VCO. With a single variable reference frequency, the PLL/VCO can provide a local oscillator (LO) between 750 MHz and 1150 MHz.
This broadband direct-conversion transmitter (analog baseband in, RF out) supports RF frequencies from 30 MHz to 2.2 GHz using a phase-locked loop (PLL) with an on-chip broadband voltage-controlled oscillator (VCO). Unlike modulators that use a divide-by-1 local oscillator (LO) stage, harmonic filtering of the LO is not required as long as the LO inputs to the modulator are driven differentially. The ADF4351 provides differential RF outputs and is, therefore, an excellent match. This PLL-to-modulator interface is useful for all I/Q modulators and I/Q demodulators that contain a 2XLO-based phase splitter.
This PLL circuit uses a 13-GHz fractional-N synthesizer, wideband active loop filter, and VCO, to achieve phase settling time of less than 5 μs to within 5° for a 200-MHz frequency jump. The performance is achieved using an active loop filter with 2.4-MHz bandwidth. This wideband loop filter is enabled by the 110-MHz maximum frequency of the ADF4159’s phase-frequency detector (PFD); and the 145-MHz gain-bandwidth product of the AD8065 op amp. The AD8065 can operate on a 24 V supply voltage, allowing control of most wideband VCOs having tuning voltages from 0 V to 18 V.
This high-performance phase locked loop (PLL) uses high-speed clock buffers and low-noise LDOs to maintain low phase noise even at low reference and RF frequencies. For example, the ADF4106 PLL specifies a 20-MHz minimum reference frequency and a 500-MHz minimum RF input frequency. This frequency range can be lowered to a 10-MHz reference frequency and a 100-MHz RF input frequency using additional clock buffers.
This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). It supports RF frequencies from 500 MHz to 4.4 GHz using a phase-locked loop (PLL) with a broadband, integrated voltage-controlled oscillator (VCO). Harmonic filtering of the local oscillator (LO) from the PLL ensures excellent quadrature accuracy, sideband suppression, and low EVM. Low noise, low dropout regulators (LDOs) ensure that the power management scheme has no adverse impact on phase noise and EVM. This combination of components represents industry leading direct conversion transmitter performance over a frequency range of 500 MHz to 4.4 GHz.
Whether an IQ modulator is used in a direct conversion application or as an upconverter to a first intermediate frequency (IF), some gain is generally applied directly after the IQ modulator. This circuit note describes how to choose an appropriate driver amplifier to provide the first stage of gain at the output of an IQ modulator. This circuit uses the ADL5375 IQ modulator and the ADL5320 driver amplifier, which are well matched from a system performance level. Because these devices are well matched in terms of their dynamic ranges, a simple direct connection between the IQ modulator and the RF driver amplifier is recommended without any need for attenuation between the devices.
This band-pass receiver front-end is based on the ADL5565 ultralow-noise differential amplifier driver and the AD9642 14-bit, 250-MSPS analog-to-digital converter (ADC). The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB. The overall circuit has a bandwidth of 18 MHz with a pass-band flatness of 3 dB. With a 127-MHz analog input, it features 71.7-dBFS signal-to-noise ratio (SNR) and 92-dBc spurious-free dynamic range (SFDR). The sampling frequency is 205 MSPS, thereby positioning the IF input signal in the second Nyquist zone between 102.5 MHz and 205 MHz.
This circuit provides a 16-bit, 250-MSPS, narrow-band, high-IF receiver front-end with an optimum interface between the ADL5565 differential amplifier with high input bandwidth, low distortion, and high output linearity and the AD9467 buffered-input 16-bit, 250-MSPS ADC with 75.5-dBFS SNR and 98‑dBFS. The systematic procedure for designing the interface circuit and antialiasing filter described here maintains high performance and ensures minimal signal loss. A resonant approach is used to design a maximally flat Butterworth fourth-order band-pass filter with 200-MHz center frequency.
This circuit is a 65-MHz bandwidth receiver front
end based on the
ADL5565 ultrahigh dynamic range differential amplifier driver and the
16-channel, 14-bit, 65-MSPS, Pipelined ADC has serial LVDS interface
The AD9249 includes 16 ADCs and a buffered voltage reference in a single package. Each channel includes a sample-and-hold, a 14-bit, 65-MSPS ADC, and an LVDS interface. Functionally complete, it only requires a power supply and a sample rate clock for full performance operation. Optimized for outstanding dynamic performance, low power, small size, and ease of use, no external reference or driver components are required for many applications. It automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. Programmable features including clock and data alignment and digital test pattern generation maximize flexibility and minimize system cost. Operating with a 1.7-V to 1.9-V supply, the AD9249 dissipates 924 mW in ANSI-644 mode, 869 mW in reduced-range mode, 199 mW in standby mode, and 2 mW in power-down mode. Available in an RoHS-compliant 144-ball CSP-BGA package, it is specified from –40°C to +85°C and priced at $113.86 in 1000s.
8-channel, 14-bit, 65-MSPS, Pipelined ADC has serial LVDS interface
The AD9681 includes eight ADCs and a buffered voltage reference in a single package. Each channel includes a sample-and-hold, a 14-bit, 125-MSPS ADC, and an LVDS interface. Functionally complete, it only requires a power supply and a sample rate clock for full performance operation. Optimized for outstanding dynamic performance, low power, small size, and ease of use, no external reference or driver components are required for many applications. It automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. Programmable features including clock and data alignment and digital test pattern generation maximize flexibility and minimize system cost. Operating with a 1.7-V to 1.9-V supply, the AD9681 dissipates 879 mW in ANSI-644 mode, 825 mW in reduced-range mode, 485 mW in standby mode, and 2 mW in power-down mode. Available in an RoHS-compliant 144-ball CSP-BGA package, it is specified from –40°C to +85°C and priced at $197.20 in 1000s.
16-bit, 1600-MSPS TxDAC+ Digital-to-Analog Converter
The AD9139 16-bit, 1600-MSPS TxDAC+® digital-to-analog converter enables multicarrier signal generation at frequencies up to Nyquist. Optimized for direct-conversion transmit applications, it includes 1×/2× interpolation, a high-speed interface, sample error detection, and parity detection. The 3-wire serial port interface facilitates programming/readback of many internal parameters. The full-scale output current can be programmed in the 9‑mA to 33-mA range. Operating on 1.8-V and 3.3-V supplies, the AD9139 dissipates 1.15 W at 1600 MSPS, 440 mW at 614 MHz, and 57.3 mW in power-down mode. Available in a 72-lead LFCSP package, it is specified from –40°C to +85°C and priced at $25.87 in 1000s.
Ultralow-noise, high PSRR Regulators provides 800-mA output current
The ADM7150 and ADM7151 low-dropout linear regulators operate from 4.5 V to 16 V and provide up to 800 mA of output current. Using an advanced proprietary architecture, they provide high power supply rejection, low noise, and excellent transient response with a 10-μF ceramic output capacitor. The ADM7150 is available in 16 fixed-output-voltage versions between 1.5 V and 5.0 V. The output voltage of the ADM7151 can be set to any voltage between 1.5 V and 5.1 V with two external resistors. It is available in two models that optimize power dissipation and PSRR as a function of input and output voltage. Typical output noise is 1.0-μV rms from 100 Hz to 100 kHz and 1.7-nV/√Hz noise spectral density above 10 kHz. The regulators offer an ideal power solution for PLLs, microwave VCOs, PLLs with integrated VCOs, wideband RF transceivers, clocks, high-speed and precision ADC/DACs, and AFEs. The low output noise spectral density significantly reduces phase noise when powering VCO circuits, and reduces jitter when powering clocks, OCXO, and clock distribution devices. The small package provides a compact solution with excellent thermal performance. Available in 8-lead LFCSP and SOIC packages, the ADM7150/51 are specified from –40°C to +125°C and priced at $3.64 in 1000s.
30-MHz to 4.5-GHz RF Detector has 45-dB dynamic range
The ADL5506 complete, low-cost RF detector provides a 45-dB dynamic range over the 30-MHz to 4.5-GHz frequency range. Its high sensitivity allows measurement of low power levels, thus reducing the amount of power that needs to be coupled to the detector. The output, proportional to the logarithm of the input power level, is scaled to 18 mV/dB at 900 MHz, increasing from 0.14 V to 1 V as the input signal increases from 1.25 mV rms (−45 dBm) to 224 mV rms (0 dBm). For convenience, the signal is internally ac-coupled, using a 5-pF capacitor and a broadband 50-Ω match. This high-pass coupling determines the lowest operating frequency and allows the source to be dc grounded. Intended for use in a wide variety of wireless terminal devices, the detector provides a wide dynamic range, high accuracy, and excellent temperature stability. Operating with a single 2.5-V to 5.5-V supply, the ADL5506 consumes 3.8 mA when enabled and 1 µA when disabled. Available in a 6-ball WLCSP package, it is specified from –40°C to +85°C and priced at $1.27 in 1000s.
200-MHz to 6-GHz RMS Power Detector has 35-dB dynamic range
The ADL5903 TruPwr™ rms-responding power detector provides a 35-dB dynamic range over the 200-MHz to 6-GHz frequency range. It can determine the true power of a high-frequency signal with a complex modulation envelope, including large crest factor signals such as GSM, CDMA, W-CDMA, TD-SCDMA, and LTE modulated signals. Its single-ended input is matched to 50-Ω source. The output, proportional to the logarithm of the rms value of the input, is scaled to 35.5 mV/dB at 900 MHz. The ripple-free transfer function is extremely stable over temperature. Operating with a single 3.0-V to 5.25-V supply, the ADL5903 consumes 3 mA when enabled and 100 µA when disabled. Available in an 8-lead LFCSP package, it is specified from –55°C to +125°C and priced at $2.35 in 1000s.
RF Agile Transceiver
The AD9361 high-performance, highly integrated RF agile transceiver offers programmability and wideband capability that make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. Operating in the 70 MHz to 6.0 GHz range, with channel bandwidths from 200 kHz to 56 MHz, the transceiver supports most licensed and unlicensed bands. Available in a 10-mm × 10-mm, 144-ball CSP_BGA package, the AD9361 is priced at $175.00 in 1000s.
12-bit Measurement and Control System
AD7294-2 integrates all of the functions required
for monitoring and control of current, voltage, and temperature, allowing
precise control of a cellular base-station’s power amplifier. It is also
useful in automotive, industrial-control, RF-transmission, and other
general-purpose applications. It comprises two low-voltage, high-side
current-sense amplifiers—with up to 59.4-V compliance, an internal
temperature sensor, two thermal-diode temperature-sensor inputs, and four
uncommitted analog inputs—all multiplexed into a 12-bit, 3-μs
successive-approximation ADC. It also includes a precision voltage
reference, four 12-bit voltage-output DACs, limit registers for alarm
functions, and an I2C interface. Available in a 64-lead TQFP
Jonathan Harris, Interleaving Spurs: Let’s Look at the Math, Planet Analog, 2013-09-17
Ray Sun, How to Design and Debug a Phase-Locked Loop (PLL) Circuit, Analog Dialogue, 2013-09-04
Jonathan Harris, Interleaving Spurs: Bandwidth Mismatches, Planet Analog, 2013-08-29
Yi Zhang and Assaf Toledano, High-Speed DACs Fuel Multiband Transmitters, Microwaves & RF, 2013-08-22
Ashraf Elghamrawi, High Performance Driver Amplifiers, Microwave Journal, 2013-02-14
T.V.B. Subrahmanyam and Mohammed Chalil,
The Successful Implementation of High-Performance Digital Radio, Analog
Daniel Fague and Sara Nadeau, RF DACs simplify power and space in downstream cable transmitter systems, EDN, 2012-12-15
Robert Brennan, High-Performance 13 GHz PLL Synthesizer, Microwave Journal, 2012-11-01
Eamon Nash, Problem Solving To Make RF And Mixed Signal Components Speak The Same Language, RF Globalnet, 2012-10-03
Gil Engel, Dan Fague and Assaf Toledano, RF Digital-to-Analog Converters Enable Direct Synthesis of Communications Signals, IEEE Communications, 2012-10-01
Eamon Nash and Ashraf Elghamrawi, RF Component Integration – Saving Space in High Performance Applications, High Frequency Electronics, 2012-09-18
Ken Gentile and David Brandon, DDS Clocks To 3.5 GHz, Microwaves & RF, 2012-09-01
Solving the Elusive Baseband to Antenna Problem using RFDAC Technology - This webinar will explore RF transmitter architectures, concentrating on the direct-to-RF architecture enabled by RFDAC technology. Aspects of the direct-to-RF transmitter system design will be explored including gain, signal bandwidth, digital signal processing requirements, frequency planning, thermal noise, clock synthesis + phase noise, harmonics, sampling images, pre-distortion techniques, and deterministic latency.
The Evolving Architecture of Military Communication Systems -- This webcast explores the different bands of Military Communications, and the advantages and disadvantages of each. We talk briefly about the shift toward software defined radios (SDR) and what that means for today’s system designers. We talk about traditional Tx/Rx signal chains for these radios, where they are heading in the future, and the key analog and mixed-signal technology that is driving these changes.
Fundamentals of Data Conversion in Receivers - This webinar examines a contemporary receive signal chain and takes a close look at selecting suitable data converters, their key specifications, and the tradeoffs that must be made.
Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS) – This concludes our two-part series on frequency synthesis with an introduction to direct digital synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
Fundamentals of Frequency Synthesis, Part 1: Phase Locked Loops – The first of a two-part series on frequency synthesis, with an introduction to phase locked loops (PLLs). This webcast looks at the need for frequency generation; techniques from the past, present, and future; how to assess the performance of a frequency synthesizer; and real world applications. Particular attention will be focused on phase locked loops as frequency synthesizers.
Solutions for Fitting High Performance RF Signal Chains into Small Spaces - This webinar will present the current state of integration of RF IC technology, with a focus on the challenges that non-handset-based wireless equipment designers face as they strive for more functionality in smaller spaces, sometimes with the added headache of having to implement broadband transceivers that can be reused at multiple frequencies.
Fundamentals of the RF Transmission and Reception of Digital Signals - Digital Modulation is an important topic for RF designers because most modern day transceivers transmit and receive digitally modulated data. In this webcast, part of ADI's continuing FUNDAMENTALS OF DESIGN series we will introduce you to the challenges—and solutions—for digital modulation. This webcast is a great way for beginners to get introduced to this vital communications standard or for veteran RF designers learn what's new in the field.
Copyright 1995- Analog Devices, Inc. All rights reserved.