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These engineer-to-engineer and application notes, published within the past 12 months, are listed in chronological order.
Power supply sequencing is required for microcontrollers, field programmable gate arrays (FPGAs), digital signal processors (DSPs), analog-to-digital converters (ADCs), and other devices that operate from multiple voltage rails. These applications typically require that the core and analog blocks be powered up before the digital input/output (I/O) rails, although some designs may require other sequences. Proper power-up and power-down sequencing can prevent both immediate damage from latch-up and long-term damage from electrostatic discharge (ESD). In addition, sequencing the supplies staggers the inrush current during power-up, an especially helpful technique in applications operating from current-limited supplies. This Application Note discusses the advantages and disadvantages of using discrete components to sequence the power supplies and describes a simple, yet effective, method of achieving sequencing by using the internal precision enable pins of the ADP5134, which combines two 1.2 A buck regulators with two 300 mA low dropout (LDO) regulators. It also describes sequencer ICs that may be useful for applications that require more accurate and flexible sequencing.
This Application Note describes how to apply the ADE7912/ADE7913 isolated sigma-delta ADCs to measure analog 4-mA to 20-mA current loops. Current loops implement a robust sensor standard, so many industrial process control applications still employ them for analog signaling. The signaling current flows through all components, with the same current flowing even if the terminations are less than perfect, and all loop components drop voltage due to the current flowing through them. The signaling current is not affected by these voltage drops as long as the supply voltage is greater than the sum of the drops around the loop at the maximum current.
This Application Note shows how to enable the new 4:2:0 feature on the ADV8005 video signal processor and ADV7625/ADV7626/ADV7627 HDMI transceivers. This feature allows receiving and transmitting ultra-HD video with a 60-Hz refresh rate (4k × 2k at 60 Hz) using a 3-GHz bandwidth. The newly introduced format reduces the chroma information for YCrCb, but increases the luma bandwidth. In the 4:2:0 format, two luma samples are sent for one chroma sample, reducing the number of video pixels sent per line.
The ADE7854A/ADE7858A/ADE7868A/ADE7878A are enhanced versions of the ADE7854/ADE7858/ADE7868/ ADE7878 energy measurement ICs. This Application Note describes the differences between these products and is recommended for use alongside the data sheet.
Applications such as bipolar amplifiers, optical modules, CCD bias, and OLED displays usually require a negative output voltage from a positive input voltage. Designers of power management systems need versatile switching controllers and regulators that allow them to solve these power management challenges. The ADP2441/ADP2442 switching regulators provide synchronous buck functionality, ranging from a 36 V input voltage down to 0.6 V output voltage at up to 1 A with a switching frequency range from 300 kHz to 1 MHz. Although targeted for synchronous step-down applications, their versatility allows them to realize an inverting buck boost topology, which can generate a negative output voltage from a positive input voltage, without additional cost, component count, or solution size. This Application Note describes how to implement a synchronous inverting buck boost topology to generate negative output voltages from positive input power supplies.
Configurable output ranges reduce the need for multiple product variants to support various range options. This circuit uses the AD5422 16-bit, serial input, unipolar/bipolar voltage and current output DAC to provide voltage output ranges of 0 V to 5 V, 0 V to 10 V, −5 V to +5 V, or −10 V to +10 V with a 10% overrange capability; a current output, accessed from a separate pin, can provide 4 mA to 20 mA, 0 mA to 20 mA, or 0 mA to 24 mA ranges. The current and voltage output pins can be connected together by adding a buffer amplifier or switch to prevent a current leakage path through an internal resistor when the device is in current output mode.
Current sense amplifiers are used to amplify small differential signals in the presence of large common-mode voltages, to measure the voltage across a shunt resistor, for example. Current sense amplifiers can operate with supply voltages as low as 1.8 V and withstand input common-mode voltages as high as 600 V. Many applications, including H-bridge motor drivers, solenoid controllers, and dc-to-dc switching converters, have common-mode voltages that vary as a function of time. An ideal current sense amplifier does not react to the input common-mode variation, but real current sense amplifiers have finite common-mode rejection, typically specified at about 100 μV/V (80 dB) at dc. This Application Note focuses on the common-mode step response of current sense amplifiers.
Blood analyzers, in-vitro diagnostic systems, and other chemical analysis applications require fluid transfer from one vessel to another. These systems must efficiently aspirate samples from cuvettes or reagents from bottles. Lab-based systems that process large numbers of samples must process them as quickly as possible. To minimize the impact of probe motion on processing time, the probes used for aspiration must move at high speed. Moving the probe efficiently requires accurate knowledge of the location of the probe in relation to the surface of the fluid being drawn. This Application Note demonstrates how a capacitance-to-digital converter (CDC) can be used to determine the probe location with a high level of confidence.
The evaluation board for the AD9129 14-bit, 5.6-GSPS RF digital-to-analog converter uses power supply filters to guarantee optimal performance. This 3-page Application Note explores the effects of removing most of the filter components. All ferrite beads on the board were removed, as well as the majority of the capacitors on the power supplies. Phase noise, noise spectral density (NSD), spurious-free dynamic range (SFDR), intermodulation distortion (IMD), and adjacent channel leakage ratio (ACLR) performance were all measured to demonstrate the effect of removing the filter components. The measurement results showed that the ferrite beads improved close-in phase noise at 20 Hz offset by approximately 5 dB, as well as single-tone IMD by up to 5 dB. Most of the capacitors proved to be redundant, however. The decoupling capacitors improved the ACLR for 6 MHz carriers by 5 dB; and the capacitor arrays improved the ACLR for 6 MHz carriers by approximately 6 dB and the NSD by approximately 1 dB. Removing all of the other the capacitors did not affect the performance.
This 4-page Application Note describes a protocol for programming the flash memory in the ADuMC320 precision analog microcontroller, which incorporates high performance analog and digital peripherals, an ARM Cortex-M3 processor, and flash memory. Its MDIO interface can operate at up to 4 MHz, simultaneously executing from one flash block and writing/erasing the other flash block.
This 8-page Application Note describes a reference design that improves the overall link budget by extending the range of the ADF7023 ISM band transceiver by almost 20 dB. In a non-interference-limited line-of-sight scenario, this equates to a range increase of approximately six to seven times. The design, which consists of an ADF7023 transceiver and an RFFM6901 front-end module, is suitable for operation in the 902 MHz to 928 MHz ISM band and complies with FCC regulations.
This 11-page Application Note specifies the EEPROM programming and calibration for the ADP1050 and ADP1051 digital controllers for isolated power supplies during power supply manufacturing. First, the hex file used for EEPROM programming is generated by the GUI software in the power supply development stage. Second, using the generated hex file, the EEPROM can be programmed. Finally, the calibration procedure is presented.
This 18-page Application Note answers a series of frequently asked questions about digital potentiometer (digiPOT) products. It includes general questions as well as specific questions, including product-specific questions. In addition, it provides digiPOT configuration information.
The ADIS16445 and ADIS16448 are low profile, fully calibrated, MEMS inertial measurement units (IMU). This 4-page Application Note provides mechanical guidelines for mounting the IMU package, which provides four mounting holes, with recessed mounting ledges that help manage the overall height of the attachment hardware. The mounting holes provide enough clearance for M2 × 0.4 mm or 2-56 machine screws.
The ADE7912 and ADE7913 isolated 3-channel, Σ-Δ ADCs target polyphase energy metering applications using shunt current sensors. The devices can be used to sense dc signals, however, so this 5-page Application Note presents their dc measurement performance. In energy metering applications, the current channel is used to sense the voltage across shunt current sensors and the voltage channels are used to measure voltages across resistor dividers. From a dc measurement perspective, this separation is not meaningful because every channel can be used to sense dc signals. This application note describes the performance when dc signals are applied at the inputs of the three Σ-Δ ADCs.
This 7-page Application Note describes using the AD5755 and other similar industrial DACs in applications that do not require the dynamic power control (DPC) feature. DPC operates by sensing the load on the current output pin and supplying only the power that is required. To achieve this, the DAC controls a dc-to-dc converter to step up a 5-V supply to between 7.4 V and 29.5 V. DPC is particularly useful in systems with wide load ranges, including a short-circuit to ground, where all power generated by the supply is dissipated on chip. In non-DPC systems, this results in higher IC and system temperatures. Low-power applications may not require dynamic power control. In these cases, the dc-to-dc converter can be excluded from the design, reducing the number of external components. This is useful for space-constrained applications that require four channels. Instead of using the dc-to-dc converter, an external PMOS can limit on-chip power dissipation, or the DAC can be powered directly, with all power dissipated on chip.
This Application Note details the cyclic redundancy code (CRC) used in the ADAS1000 electrocardiogram front end. Error detection enables the receiver of a message to determine whether the message has been corrupted. To do this, the ADAS1000 constructs a code—called a checksum—that is a function of the message and appends it to the message. The CRC algorithm treats the message as an enormous polynomial, dividing it by another fixed polynomial using modulo-2 arithmetic for the coefficients. The remainder from this division is the checksum. Upon receipt of the message, the receiver can perform the same division and compare the remainder with the checksum. This note describes how the checksum is calculated.
Packages for the ADIS16375, ADIS16480, ADIS16485, and ADIS16488 include four 2.4-mm mounting holes, an aluminum housing, and a 2-row, 24-pin, 1-mm pitch electrical interface connector. This 4-page Application Note provides tips for system-level installation.
This 7-page Application Note describes the Reed-Solomon firmware module, which contains both forward error correction and advanced encryption standard (AES) encryption, for the ADF7023 transceiver. Reed-Solomon encoding appends check symbols to the transmitted data. When received, these symbols detect the presence of errors and correct them in the received data. The firmware module is flexible, allowing the user to select values that enable correction of up to five error bytes within a packet. Encoded packets are resilient to burst and random errors; their coding gain improves link margin.
This 11-page Application Note describes the radio performance of the ADF7021-N transceiver when configured for operation according to the wireless meter-bus (WM-Bus) standard, focusing on key receiver parameters applicable to the 2.4 kbps and 4.8 kbps modes of operation. These parameters are packet error rate (PER) over power, sensitivity over carrier frequency error, blocking, and adjacent channel selectivity.
The ADV7850, the first complete audio/video front-end device developed by Analog Devices, targets the professional and consumer video markets. The device incorporates a frame checker block that employs cyclic redundancy checking (CRC). This 3-page Application Note outlines the background of the frame checker function and details how it is utilized.
ADI provides symbols and footprints for components in binary Xlator (.bxl) files that were created using the Ultra Librarian tool offered by Accelerated Designs, Inc. A free version of this tool is available on the Accelerated Designs website. Once the .bxl file is opened, the Ultra Librarian Reader allows the footprint and symbol to be exported to one of many CAD toolsets, including Cadence® Allegro® Allegro®OrCAD®, Accel15/PCAD 2xxx/Altium6, Mentor PADS®, PowerPCB, and Zuken, Inc., CADSTAR®. These toolsets cover 97% of CAD users.
This 2-page Application Note outlines the usage of the ADV7619 HDMI® video receiver for the 4:2:0 HDMI stream 4k × 2k at 60 Hz. The ADV7619 can receive 4:2:0 video streams in the same way it receives 4:4:4 data in 4k × 2k modes. To enable this, set OP_FORMAT_SEL to the value of 0x54 and set all other I2C writes in the same way as for 4k × 2k 4:4:4 video mode. Because the ADV7619 works only as a bypass for 4k × 2k modes, it outputs samples as they are received without providing color space conversion (CSC). The receiver bypasses CP core and thus neither CSC nor up-conversion/down-conversion of video standard is available.
High-performance data acquisition signal chains used for spectroscopy, magnetic resonance imaging (MRI), and gas chromatography—and vibration, oil/gas, and seismic systems demand a state-of-the-art, high dynamic range (DR) while addressing difficult thermal design, space, and cost challenges. One way to achieve a higher dynamic range is to oversample the converter to accurately monitor and measure both small and large input signals from the sensors. Other ways include using programmable-gain amplifiers or operating multiple ADCs in parallel, using digital postprocessing to average the result. These methods may be cumbersome or impractical to implement in some systems, mainly due to power, space, and cost constraints. This 4-page Application Note focuses on the oversampling of high-throughput, 5‑MSPS, 18-bit/16-bit precision successive approximation register (SAR) converters by implementing a straightforward averaging of ADC output samples to increase the dynamic range.
Heterodyne radios, such as the ADF7023 family of transceivers, use a mixer to downconvert received radio frequency (RF) signals to an intermediate frequency (IF). Interfering signals, called interferers, that lay on the image frequency are also mixed down to the wanted frequency. This desensitizes the receiver, resulting in blocking on the wanted channel. In theory, an ideal transceiver, which employs an IQ receive architecture, can be configured to eliminate the image frequency mixing onto the wanted channel. This theory assumes that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a firmware download module, until the quadrature signals are optimally balanced, providing maximum image rejection. This 6-page Application Note describes the fully autonomous image rejection (IR) calibration firmware download module for the ADF7023 transceiver IC. With minimum user input, this firmware optimizes the image rejection with a default configuration completely autonomously.
This 4-page Application Note provides information on the built-in packet error rate (PER) test mode on the ADF7023 and ADF7023-J. This mode helps the user to set up a communication link and test its quality. Up to 65,535 packets can be transmitted with a programmable delay between packets. The packet stored in packet RAM is transmitted each time. If the cyclic redundancy check (CRC) is correct, the receiver determines it has correctly received a packet.
When the ADF7023 receives a packet in packet mode, it stores the data in a linear sequence in the packet RAM. Prior to transmission, the data to be transmitted is written to the packet RAM in a linear sequence, as described in the ADF7023 data sheet. The ADF7023 packet RAM is 240 bytes long. If the packet length is greater than 240 bytes, additional measures are required. This 4-page Application Note describes a method for handling longer packet lengths on the ADF7023, up to a maximum length of 65,535 bytes, via a rolling buffer mechanism. This method reuses and renames several registers of the ADF7023.
Industrial measurement and control systems often need to interface to sensors while operating in noisy environments. Because sensors typically generate very small electrical signals, extracting their output from the noise can be challenging. Applying signal conditioning techniques such as amplification and filtering increases the system sensitivity and simplifies signal extraction. The signal can be scaled and shifted to take full advantage of high-performance ADCs. This 7-page Application Note introduces a general-purpose precision signal conditioning front-end that can close the gap between sensors and high-resolution ADCs. The circuit is analyzed to find its noise contribution, ambient noise rejection, and ability to perform highly sensitive measurements.
Various applications require the generation of two or more sinusoidal or square wave signals with a known phase relationship between them. The AD9915 DDS IC is capable of providing such signals. This 6-page Application Note offers detailed instructions on how to synchronize two or more of these devices and considers possible sources of phase error.
This 8-page Application Note shows a basic configuration in which a field-programmable gate array (FPGA) is used as a signal source, producing sync timing and a video pattern, and the ADV7511/ADV7511W/ADV7513 are configured to output a valid High-Definition Multimedia Interface (HDMI®) or digital visual interface (DVI) stream—focusing on the most basic example to illustrate ways of generating a valid video stream.
This 16-page application note explains the process of calibrating a 3-phase energy meter built around the ADE7978 and ADE7932/ADE7933 isolated metering chipset. A single 3.3-V supply powers the chipset. Three isolated ADCs sense phase currents using shunts and phase-to-neutral voltages using resistor dividers. A microcontroller manages the ADCs via I2C or SPI.
Heterodyne radios, such as the ADF7021 family of transceivers, use a mixer to down convert received RF signals to an intermediate frequency (IF). The output of the mixer contains the wanted frequency component along with an unwanted component at the image frequency. Unwanted signals present at the image frequency can degrade receiver sensitivity, resulting in loss of signal on the wanted channel. In theory, transceivers employing an I/Q receive architecture can be configured to infinitely reject the image frequency, assuming that the gain balance and the phase orthogonality of the mixer quadrature paths are perfectly aligned. In practice, some imbalance exists due to imperfections in the mixer. The image calibration process adjusts the gain and phase of the mixer via a digital control register until the quadrature signals are optimally balanced, providing maximum image rejection. This 11-page Application Note provides information on the mechanism that generates the image frequency and describes how image calibration can be implemented on the ADF7021, ADF7021-N, and ADF7021-V.
The AD5933 and AD5934 high precision impedance converter network analyzers are finite systems with some limitations. This 11-page Application Note explains the optimum measurement setup.
This 11-page Application Note describes a reference design using the ADF7241/ADF7242 highly integrated, low power, high performance transceiver and the SE2431L fully integrated RF front-end. The ADF7241 and ADF7242, which operate in the global 2.4-GHz ISM band, provides flexibility, robustness, ease of use, and low current consumption. They support the IEEE 802.15.4-2006 2.4‑GHz PHY requirements. The ADF7242 also supports proprietary GFSK/FSK/GMSK/MSK modulation schemes in both packet and data streaming modes. The Skyworks SE2431L, designed for 2.4 GHz applications, provides ease of use and maximum flexibility, with fully matched 50 Ω input and output, integrated interstage matching, harmonic filter, and digital controls that are compatible with 1.6 V to 3.6 V CMOS levels.
This 17-page Application Note introduces the main features of the ADSP-CM408F’s analog-to-digital converter controller (ADCC), focusing on current feedback systems in high performance motor control applications. It highlights key capabilities of the analog-to-digital converter (ADC) module, guides configuration for motor control applications, and provides code samples for the ADCC drivers.
This 6-page Application Note describes a technique for autonomously detecting and capturing shock events using a low power, high-g, 3-axis digital MEMS accelerometer with minimal intervention from the host processor. The accelerometer can be programmed to monitor single or double (primary and secondary) shocks along any combination of X, Y, and/or Z axes. In addition, the entire shock profile can be captured for further analysis using an integrated 32 sample memory.
This 16-page Application Note introduces the main features of the ADSP-CM40xF’s SINC filters, focusing on high performance motor control applications. It highlights the key capabilities of the SINC filter and shows usage of the SINC filter drivers. Each SINC filter is part of a complete motor current feedback subsystem that includes a current shunt, a modulator to digitize and isolate the signal, and the SINC filter to decode the bit stream and present it to the controller.
This 3-page Application Note helps designers to achieve frequency stability and accuracy for the external oscillators used with video decoders, which typically require a 28.63636-MHz crystal with 50-ppm frequency stability in fundamental mode.
This 4-page Application Note describes the automatic and manual scaling algorithms used in the ADV7186 video decoder. Upscaling changes a low resolution video input to a higher resolution video output; downscaling changes a high resolution video input to a lower resolution video output to satisfy the back end device without the need for external memory.
This 6-page Application Note describes how to connect evaluation boards to collect high accuracy digital temperature readings from the ADT7310/ADT7410 sensors using Cortex-M3® based precision analog microcontrollers, such as the ADuCM360. Example code shows how the microcontroller and temperature sensor can communicate using I2C and SPI interfaces.
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