JESD204 Serial Interface JEDEC Standard for Data Converters

JESD204 Serial Interface JEDEC Standard for Data Converters

The JESD204 and the JESD204B revision data converter serial interface standard was created through the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects simplifies layout and allows smaller form factor realization without impacting overall system performance. These attributes are important to address the system size and cost constraints of a range of high speed ADC applications, including wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) transceiver architectures, software-defined radios, portable instrumentation, medical ultrasound equipment, and Mil/Aero applications such as radar and secure communications. Analog Devices is an original participating member of the JEDEC JESD204 standards committee and we have concurrently developed compliant data converter technology and tools, and a comprehensive product roadmap to fully enable our customers to take advantage of this significant interfacing breakthrough.

Learn more about JESD204B. Get the JESD204B information you need by downloading one document. Download the JESD204B Survival Guide. (pdf)


Engineer Zone

JESD204-Compatible Data Conversion Products

  • AD9656

    The AD9656 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

    The ADC requires a single 1.8 V MoreRead more

    AD9656 Diagram

    - Quad, 16-Bit, 125 MSPS JESD204B 1.8 V Analog-to-Digital Converter

  • AD9250

    The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.

    The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety MoreRead more

    AD9250 Diagram

    - 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter

  • AD6673

    The AD6673 is an 11-bit, 250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.

    The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC MoreRead more

    AD6673 Diagram

    - 80 MHz Bandwidth, Dual IF Receiver

  • AD9683

    The AD9683 is a 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9683 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.

    The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC core features wide bandwidth inputs supporting a variety of MoreRead more

    AD9683 Diagram

    - 14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter


Three-Part Video Series

JESD204B and Why It Should Matter to You (Part 1 of 3)

 

Rapid JESD204B Data Converter-to-FPGA Prototyping (Part 2 of 3)

Implementing JESD204B A/D Converters-to-FPGA Designs (Part 3 of 3)

Technical Webcast Series

JESD204B High-speed Serial Data Interface Analog Devices, Inc., Staff Applications Engineer Del Jones, provides in-depth explanation and design analysis of the key aspects of JESD204B high-speed serial interface technology. JESD204B brings compelling advantages in interface standardization and simplification, higher data rate capability, multi-channel synchronization, and deterministic latency, and it is available today in ADI’s latest high-speed ADC,s DAC’s and wideband RF transceivers. In four technical webinar sessions, you’ll get the essentials for understanding and implementing this new interface technology.

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