JESD204 Serial Interface JEDEC Standard for Data Converters

JESD204 Serial Interface JEDEC Standard for Data Converters

The JESD204 data converter serial interface standard was created through the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects simplifies layout and allows smaller form factor realization without impacting overall system performance. These attributes are important to address the system size and cost constraints of a range of high speed ADC applications, including wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) transceiver architectures, software-defined radios, portable instrumentation, medical ultrasound equipment, and Mil/Aero applications such as radar and secure communications. Analog Devices is an original participating member of the JEDEC JESD204 standards committee and we have concurrently developed compliant data converter technology and tools, and a comprehensive product roadmap to fully enable our customers to take advantage of this significant interfacing breakthrough.

Learn more about JESD204B. Get the JESD204B information you need by downloading one document. Download the JESD204B Survival Guide. (pdf)

JESD204B Survival Guide

Engineer Zone

JESD204-Compatible Data Conversion Products

  • AD9250

    The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.

    The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety MoreRead more

    AD9250 Diagram

    - 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter

  • AD6673

    The AD6673 is an 11-bit, 250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.

    The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC MoreRead more

    AD6673 Diagram

    - 80 MHz Bandwidth, Dual IF Receiver

  • AD9683

    The AD9683 is a 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9683 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.

    The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC core features wide bandwidth inputs supporting a variety of MoreRead more

    AD9683 Diagram

    - 14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter

  • AD6677

    The AD6677 is an 11-bit, 250 MSPS, intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.

    The device consists of a high performance analog-to-digital converter (ADC) and a noise shaping requantizer (NSR) digital block. The ADC consists of a MoreRead more

    AD6677 Diagram

    - 80 MHz Bandwidth, IF Receiver


Three-Part Video Series

JESD204B and Why It Should Matter to You (Part 1 of 3)

 

Rapid JESD204B Data Converter-to-FPGA Prototyping (Part 2 of 3)

Implementing JESD204B A/D Converters-to-FPGA Designs (Part 3 of 3)

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