Features and Benefits

  • Flexible reconfigurable common platform design
    • Supports single, dual, and quad band per channel
    • Datapaths and DSP blocks are fully bypassable
    • On-chip PLL with multichip synchronization
    • External RFCLK input option for off-chip PLL
  • Support clock input frequencies up to 12 GHz
    • Maximum ADC sample rate up to 6 GSPS
    • Useable analog bandwidth to 8 GHz
  • Maximum data rate up to 6 GSPS using JESD204C
  • Noise density: −153 dBFS/Hz
  • ADC AC performance at 6 GSPS, input at 2.7 GHz, −1 dBFS
    • Full-scale sine wave input voltage: 1.475 V p-p
    • Noise figure: 25.3 dB
    • HD2: −70 dBFS
    • HD3: −68 dBFS
    • Worst other (excluding HD2 and HD3): −84 dBFS
  • Versatile digital features
    • Selectable decimation filters
    • Configurable DDC
      • 8 fine complex DDCs and 4 coarse complex DDCs
      • 48-bit NCO per DDC
      • Option to bypass fine and coarse DDC
    • Programmable 192-tap PFIR filter for receive equalization
  • Supports 4 different profile settings loaded via the GPIOx pins
  • Programmable delay per datapath
    • Receive AGC support
      • Fast detect with low latency for fast AGC control
    • Signal monitor for slow AGC control
    • Dedicated AGC support pins
  • Auxiliary features
    • Fast frequency hopping
    • ADC clock driver with selectable divide ratios
    • On-chip temperature monitoring unit
    • Flexible GPIOx pins
  • SERDES JESD204B/JESD204C interface, 8 lanes up to 24.75 Gbps
    • 8 lanes JESD204B/JESD204C transmitter (JTx)
    • JESD204B compliance with the maximum 15.5 Gbps
    • JESD204C compliance with the maximum 24.75 Gbps
    • Supports real or complex digital data (8 bit, 12 bit, 16 bit, or
      24 bit)

Product Details

The AD9207 is a dual, 12-bit, 6 GSPS analog-to-digital converter (ADC). The ADC input features an on-chip wideband buffer with overload protection. This device is designed to support applications capable of direct sampling wideband signals up to 8 GHz. An onchip, low phase noise, phase-locked loop (PLL) clock synthesizer is available to generate the ADC sampling clock, which simplifies the printed circuit board (PCB) distribution of a high frequency clock signal. A clock output buffer is available to transmit the ADC sampling clock to other devices.

The dual ADC cores have code error rates (CER) better than 2 × 10−15. Low latency fast detection and signal monitoring are available for automatic gain control (AGC) purposes. A flexible 192-tap programmable finite impulse response filter (PFIR) is available for digital filtering and/or equalization. Programmable integer and fractional delay blocks support compensation for analog delay mismatches.

The digital signal processing (DSP) block consists of two coarse digital downconverters (DDCs) and four fine DDCs per ADC pair. Each ADC can operate with one or two main DDC stages in support of multiband applications. The four additional fine DDC stages are available to support up to four bands per ADC. The 48-bit numerically controlled oscillators (NCOs) associated with each DDC support fast frequency hopping (FFH) while maintaining synchronization with up to 16 unique frequency assignments selected via the general-purpose input and output (GPIOx) pins or the serial port interface (SPI).

The AD9207 supports one or two JTx links that can be configured for either JESD204B or JESD204C subclass operation, which allows different datapath configurations for each ADC. Multidevice synchronization is supported through the SYSREF± input pins.

See the Outline Dimensions section and the Ordering Guide section of the data sheet for more information.


  • Wireless communications infrastructure
  • Microwave point to point, E-band, and 5G mmWave
  • Broadband communications systems, satellite communications
  • DOCSIS 3.1 and 4.0 CMTS
  • Electronic warfare
  • Electronic test and measurement systems

Product Lifecycle icon-recommended Recommended for New Designs

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

Evaluation Kits (2)

Documentation & Resources

  • View All (11)
  • Data Sheets (1)
  • User Guides (1)
  • FPGA Interoperability Reports (1)
  • Application Notes (1)
  • Design Notes (1)
  • Technical Articles (5)
  • Videos (1)
  • Tools & Simulations


    AD9081/AD9082/AD9986/AD9988 RFIO Models

    Keysight ADS workbook and s-parameter files for simulating the frequency response of the AD908x DAC, ADC, and CLK interfaces. See Application note AN-2065: Optimizing RF performance of the AD9081 and AD9082” for instructions on how to use the models.

    Design Tools

    MxFE JESD204 Mode Selector Tool (Rev. E)

    The JESD204B/C Mode Selector Tool is a simple command line-based Windows executable that can be used to narrow down the number of JESD204x modes to only include those modes that support the user’s specific application use case. The tool guides the user through a use case description flow chart and gives the user a small list of applicable transmit and/or receive modes to choose from. This tool is applicable to the AD9081, AD9082, AD9177, AD9207, AD9209, AD9986, and AD9988.

    Companion Transport Layer RTL Code Generator Tool (Rev. 1.0)

    This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

    JESD204x Frame Mapping Table Generator

    The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.


    ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.

    Product Recommendations

    AD9207 Companion Parts

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    Design Resources

    ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

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