Features and Benefits

  • Buffered input with −3 dB bandwidth ≥ 7.5 GHz
    • Full-scale of 1.4 V p-p with RIN = 100 Ω
    • Overload protection clamp
    • Supports dc-coupled with common-mode feedback
  • AC performance at fIN < 2.6 GHz
    • HD2 < −63 dBc and HD3 < −67 dBc
    • Small signal (−12 dBFS) noise spectral density (NSD) = −153 dBFS/Hz
  • Low code error rate (CER) < 2 × −10−15
  • Flexible ADC clocking options
    • On-chip PLL or external RF clock
  • Versatile digital features
  • Configurable digital down conversion (DDC)
    • 2 coarse complex DDCs per ADC
    • 4 fine complex DDCs per ADC
  • Programmable 192 tap FIR filter
  • Integer/fractional sample delay for digital predistortion (DPD) or IQ mismatch
  • Power consumption~ 4 W to 5.5 W
  • Automatic gain control (AGC) support with dedicated AGC support pins
    • Fast detect with low latency for fast AGC control
    • Signal monitor for slow AGC control
  • Auxiliary features
    • Fast frequency hopping
    • ADC clock driver with selectable divide ratios
    • On-chip temperature sensor
    • Programmable GPIO pins
  • JESD204B/C (Subclass 1) interface, 8 lanes
    • JESD204B compatible with the maximum 15.5 Gbps lane rate
    • JESD204C compatible with the maximum 24.75 Gbps lane rate
    • Sample/bit repeat mode for receive lane rate matching
    • Supports real or complex digital data (12-bit, 16-bit, or 24-bit)
    • Multichip synchronization
  • 15 mm × 15 mm BGA with 0.8 mm pitch

Product Details

The AD9207 is a dual, 12-bit, 6 GSPS analog-to-digital converter (ADC). The ADC input features an on-chip wideband buffer with overload protection. This device is designed to support communications applications capable of direct sampling wideband signals up to 7.5 GHz. An optional low phase noise phase-locked loop (PLL) clock synthesizer is available to generate the ADC sampling clock, simplifying printed circuit board (PCB) distribution of a high frequency clock signal. Alternatively, the CLKIN of the device can be driven directly with the ADC sampling clock (or a higher version up to 12 GHz when the internal clock divider is enabled). An optional CLKOUT buffer is available to transmit the ADC sampling clock to other devices.


  • Diversity multiband and multimode digital receivers
  • Microwave point-to-point, E-Band, and 5G mm wave
  • Broadband communications systems
  • Phased array radar and electronic warfare
  • Electronic test and measurement systems

Product Lifecycle icon-recommended Pre-Release

This product is new and engineering validation may still be underway. Quantities may be limited and design specifications may change while we ready the product for release to production.

Evaluation Kits (2)

Tools & Simulations

Design Tools

MxFE JESD204 Mode Selector Tool

The JESD204B/C Mode Selector Tool is a simple command line-based Windows executable that can be used to narrow down the number of JESD204x modes to only include those modes that support the user’s specific application use case. The tool guides the user through a use case description flow chart and gives the user a small list of applicable transmit and/or receive modes to choose from. This tool is applicable to the AD9081, AD9082, AD9177, AD9207, AD9209, AD9986, and AD9988.

Companion Transport Layer RTL Code Generator Tool (Rev. 1.0)

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

JESD204x Frame Mapping Table Generator

The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.

Product Recommendations

AD9207 Companion Parts

Recommended Power Products

Recommended Clock Distribution Device

Recommended Clock Generation Device

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Design Resources

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

Price Table Help

Evaluation Boards Pricing displayed is based on 1-piece.
Up to two boards can be purchased through Analog.com. To order more than two, please purchase through one of our listed distributors.
Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.