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User GuidesDC2609A Demo Manual
Features and Benefits
- JESD204B/C, Subclass 1 SYSREF Signal Generation
- Low Noise Integer-N PLL
- Additive Output Jitter < 6fsRMS
- (Integration BW = 12kHz to 20MHz, f = 4.5GHz)
- Additive Output Jitter 65fsRMS (ADC SNR Method)
- EZSync™, ParallelSync™ Multichip Synchronization
- –229dBc/Hz Normalized In-Band Phase Noise Floor
- –281dBc/Hz Normalized In-Band 1/f Noise
- Eleven Independent, Low Noise Outputs with Programmable Coarse Digital and Fine Analog Delays
- Flexible Outputs Can Serve as Either a Device Clock or SYSREF Signal
- Reference Input Frequency up to 500MHz
- LTC6952Wizard™ Software Design Tool Support
- –40ºC to 125°C Operating Junction Temperature Range
The LTC6952 is a high performance, ultralow jitter, JESD204B/C clock generation and distribution IC. It includes a Phase Locked Loop (PLL) core, consisting of a reference divider, phase-frequency detector (PFD) with a phase-lock indicator, ultralow noise charge pump and integer feedback divider. The LTC6952’s eleven outputs can be configured as up to five JESD204B/C subclass 1 device clock/SYSREF pairs plus one general purpose output, or simply eleven general purpose clock outputs for non-JESD204B/C applications. Each output has its own individually programmable frequency divider and output driver. All outputs can also be synchronized and set to precise phase alignment using individual coarse half-cycle digital delays and fine analog time delays.
For applications requiring more than eleven total outputs, multiple LTC6952s can be connected together using the EZSync or ParallelSync synchronization protocols.
- High Performance Data Converter Clocking
- Wireless Infrastructure
- Test and Measurement
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (3)
Features & Benefits
Demonstration circuit 2609A features the LTC6952, an Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B Support.
By default, the DC2609A is powered from two supplies. The 9V-12V supply input powers the onboard reference and VCO circuitry, along with the LTC6952 5V supply pin. The 4V-6V supply input powers the LTC6952 3.3V supply pins. A reduced power option is provided that allows the LTC6952’s output supply pins to connect to an LTC Silent Switcher® and the LTC6952 input supply pins to connect to a low noise LDO.
All differential inputs and six of the differential outputs are populated with 0.5” spaced SMA connectors. These outputs are AC-coupled with 50Ω transmission lines making them suitable to drive 50Ω impedance instruments. The remaining five differential outputs are terminated with 100Ω.
The LTC6952’s EZSync™ and SYSREF request functions are made available via the LTC6952 SPI interface or the EZS_SRQ SMA/turret connectors. The DC2609A, DC2610A, and DC2611A SMA placement was designed for ease of connection for all multi-part synchronization and SYSREF request modes.
The VTUNE and VCO SMAs can mate directly with the DC2664A VCO rider board. This options allows for a quick method to evaluate multiple VCOs.
A DC2026 USB serial controller board is used for SPI communication with the LTC6952, controlled by the supplied LTC6952Wizard™ software.
Linear Technology’s DC2026 (called the Linduino™ One) is compatible with the Arduino Uno microcontroller board. Arduino hardware consists of an Atmel microcontroller with a bootloader allowing quick in-circuit firmware updates. The software is a simple programming environment based on the AVRGCC compiler. This platform is popular because it is easy to use, both the hardware and software are open source, and it can be programmed in C. We find it an ideal way to demonstrate and distribute libraries for integrated circuits that have digital interfaces such as Inter-Integrated Circuit (I2C) and Serial Peripheral Interface (SPI). While the Linduino One is Arduino-compatible, it is not produced by the official Arduino team, and they do not receive any monetary support from this board. Please, consider supporting them by purchasing other items from: http://store.arduino.cc
Demonstration circuit 2664A is a VCO Rider Board with Loop Filter that supports the popular 0.5" × 0.5" VCO package footprint.
The DC2664A expedites evaluation of Phase-Locked Loop (PLL) devices requiring an external Voltage Controlled Oscillator (VCO). Without the DC2664A, each VCO and PLL combination requires a unique loop filter design, resulting in several PLL demo board modifications to evaluate each VCO. These board modifications are time consuming and often result in damage to either the PLL or the VCO.
The DC2664A integrates the VCO and loop filter allowing these unique designs to reside on multiple DC2664As. The DC2664A RFOUT and VTUNE SMA connections allow the user to quickly evaluate a PLL with multiple VCOs without risk of damage from multiple board modifications.
VCOs are notoriously sensitive to power supply noise and spurs. The DC2664A resolves the concern of locating a low noise and low spurious lab supply by powering the VCO with an onboard ultralow noise and ultrahigh PSRR LDO, the LT3042. A second LT3042 LDO is available on the DC2664A to power an active loop filter. Both LDOs are powered from a single supply, simplifying the number of lab supplies required to evaluate a VCO and PLL combination.
The DC2664A was designed to mate directly with the LTC6955 (DC2611A) and LTC6952 (DC2609A) demo boards.
Software & Systems Requirements
Tools & Simulations
Product Selection Guide (1)
Analog Dialogue (1)
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Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.