Features and Benefits
- Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at 2457.6 MHz
- Noise floor: −156 dBc/Hz at 2457.6 MHz
- Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output
- Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) from PLL2
- Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency up to 3200 MHz
- JESD204B/JESD204C-compatible system reference (SYSREF) pulses
- 25 ps analog, and ½ VCO cycle digital delay independently programmable on each of 14 clock output channels
- SPI-programmable phase noise vs. power consumption
- SYSREF valid interrupt to simplify JESD204B/JESD204C synchronization
- Narrow-band, dual core VCOs
- Up to 2 buffered voltage controlled oscillator (VCXO) outputs
- Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes
- Frequency holdover mode to maintain output frequency
- Loss of signal (LOS) detection and hitless reference switching
- 4× GPIOs alarms/status indicators to determine the health of the system
- External VCO input to support up to 6000 MHz
- On-board regulators for excellent PSRR
- 68-lead, 10 mm × 10 mm LFCSP package
The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B/JESD204C type) interfaces. The HMC7044 features two integer mode PLLs and overlapping on-chip VCOs that are SPI-selectable with wide tuning ranges around 2.5 GHz and 3 GHz, respectively. The device is designed to meet the requirements of GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The HMC7044 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays (FPGAs), and mixer local oscillators (LOs).
The DCLK and SYSREF clock outputs of the HMC7044 can be configured to support signaling standards, such as CML, LVDS, LVPECL, and LVCMOS, and different bias settings to offset varying board insertion losses.
- JESD204B/JESD204C clock generation
- Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
- Data converter clocking
- Microwave baseband cards
- Phase array reference distribution
Markets and Technologies
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (3)
The HMC7044 meets the requirements of multi-carrier GSM and LTE base-station designs and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The high performance dual-loop core of the HMC7044 enables the base station designer to attenuate the incoming jitter of a primary system reference clock, such as a CPRI source, with the help of the narrow-band configured first PLL loop, which disciplines an external VCXO, and generate the low phase noise, high frequency clocks with the wider-band second PLL to drive data converter sample clock inputs.
The EK1HMC7044LP10B evaluation board is a compact, easy-to-use platform for evaluating all the features of the HMC7044. A 122.88 MHz VCXO is mounted on the evaluation board to provide a complete solution. All inputs and outputs are configured as differential on the evaluation board.
Full specifications on the HMC7044 are available in the product data sheet, which should be consulted in conjunction with this user guide when working with the evaluation board.
Features & Benefits
- Simple power connection using USB connection and on-board LDO voltage regulators
- LDOs can be bypassed for power measurements
- AC-coupled differential SMA connectors
- SMA connectors for
2 reference Inputs
6 clock outputs
1 VCXO output
- Microsoft Windows®–based evaluation software with simple graphical user interface
- On-board PLL loop filter
- Easy access to digital input/output and diagnostic signals via input/output header (4 GPIOs)
- Status LEDs for diagnostic signals
- USB computer interface
The Quad-MxFE System Development Platform contains four MxFE® software defined, direct RF sampling transceivers, as well as associated RF front-ends, clocking, and power circuitry. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a 16 transmit/16 receive channel direct sampling phased array at L/S/C band (0.1 GHz to ~5GHz). The Rx & Tx RF front-end has drop-in configurations that allow for customized frequency ranges, depending on the user’s application.
The Quad-MxFE System Development Platform highlights a complete system solution. It is intended as a testbed for demonstrating multi-chip synchronization as well as the implementation of system level calibrations, beamforming algorithms, and other signal processing algorithms. The system is designed to mate with a VCU118 Evaluation Board from Xilinx®, which features the Virtex® UltraScale+™ XCVU9P FPGA, with provided reference software, HDL code, and MATLAB system-level interfacing.
In addition to the Quad-MxFE Digitizing Card, the kit also contains a 16Tx / 16Rx Calibration Board that is used to develop system-level calibration algorithms, or otherwise more easily demonstrate power-up phase determinism in situations pertinent to their own use case. The Calibration Board also allows the user to demonstrate combined-channel dynamic range, spurious, and phase noise improvements and can also be controlled via a free MATLAB add-on when connected to the PMOD interface of the VCU118.
The system can be used to enable quick time-to-market development programs for applications like:
- ADEF (Phased-Array, RADAR, EW, SATCOM)
- Communications Infrastructure (Multiband 5G and mmWave 5G)
- Electronic Test and Measurement
Features & BenefitsQuad-MxFE Digitizing Card
- Multi-Channel, Wideband System Development Platform Using MxFE
- Mates With Xilinx VCU118 Evaluation Board (Not Included)
- 16x RF Receive (Rx) Channels (32x Digital Rx Channels)
- Total 16x 1.5GSPS to 4GSPS ADC
- 48x Digital Down Converters (DDCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
- 16x Programmable Finite Impulse Response Filters (pFIRs)
- 16x RF Transmit (Tx) Channels (32x Digital Tx Channels)
- Total 16x 3GSPS to 12GSPS DAC
- 48x Digital Up Converters (DUCs) , Each Including Complex Numerically-Controlled Oscillators (NCOs)
- Flexible Rx & Tx RF Front-Ends
- Rx: Filtering, Amplification, Digital Step Attenuation for Gain Control
- Tx: Filtering, Amplification
- On-Board Power Regulation from Single 12V Power Adapter (Included)
- Flexible Clock Distribution
- On-Board Clock Distribution from Single External 500MHz Reference
- Support for External Converter Clock per MxFE
- Mates to Quad-MxFE Digitizing Card & VCU118 PMOD Interface (Cable Included)
- Provides Both Individual Adjacent Channel Loopback and Combined Channel Loopback Options
- Combined Tx Channels Out Via SMA Option
- Combined Rx Channels In Via SMA Option
- On-Board Log Power Detectors With AD5592R Output To VCU118 Over PMOD
- On-Board Power Regulation from Single 12V Power Adapter (Included)
Easy Control Tools and Platform Interfaces to Simplify Software Framework Developments:
- IIO Oscilloscope GUI
- MATLAB Add-Ons & Example Scripts
- Example HDL Builds including JESD204b/JESD204c Bring-Up
- Embedded Software Solutions for Linux and Device Drivers
- MATLAB System Applications GUI
- Multi-Chip Synchronization for Power-Up Phase Determinism
- System-Level Amplitude/Phase Alignment Using NCOs
- Low-Latency ADC-to-DAC Loopback Bypassing JESD Interface
- pFIR Control for Broadband Channel-to-Channel Amplitude/Phase Alignment
- Fast-Frequency Hopping
- Calibration Board MATLAB Driver File
- FPGA Programming MATLAB Script
The AD9208-3000EBZ supports the AD9208-3000, a 14-bit, 3GSPS dual analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed support direct RF sampling analog signals of up to 5 GHz. The 3 dB bandwidth of the ADC input is greater than 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V2EBZ data capture card, allowing users to download captured data for analysis. The device control and subsequent data analyses can now be done using the ACE software package.
The AD9208-DUAL-EBZ is a demonstration board designed to show multi-chip synchronization using JESD204B subclass1 protocol. The AD9208-3000 is a 14-bit, 3GSPS dual analog-to-digital converter (ADC). This device is designed support direct RF sampling analog signals of up to 5 GHz. The 3 dB bandwidth of the ADC input is greater than 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B type) interfaces. The LTM8074 is a 40VIN, 1.2A continuous, 1.75A peak, step-down µModule® (power module) regulator. The Silent Switcher architecture minimizes EMI while delivering high efficiency at frequencies up to 2.2MHz.
This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to easily demonstrate multi-chip synchronization using the JESD204B subclass1 protocol. The board is designed to interface directly with FPGA development boards with FMC+ (Vita57.4) connector.
Features & Benefits
Two evaluation options are available: AD9208-3000EBZ and AD9208-DUAL-EBZ.
- AD9208-3000 Features
- Full featured evaluation board for the AD9208-3000.
- Wide band Balun driven input.
- No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC connector.
- Single software interface for device control and analysis through ACE.
- AD9208-DUAL Features
- Demonstration board showing multi-chip synchronization of two AD9208 ADCs using HMC7044.
- Self contained clocking for the ADCs as well as the FPGA.
- Single external 12V supply.
- Interfaces with VCU118 or similar FPGA development board with FMC+ (Vita57.4) connector.
- Uses Analog Devices’ JESD204B IP framework.
- Low SWaP high efficiency power delivery using Silent Switcher technology.
- Full software support available Analog Devices Wiki Page.
Tools & Simulations
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Product Selection Guide (1)
Technical Articles (6)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Support & Discussions
Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.