Features and Benefits
- Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at 2457.6 MHz
- Noise floor: −156 dBc/Hz at 2457.6 MHz
- Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output
- Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) from PLL2
- Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency up to 3200 MHz
- JESD204B/JESD204C-compatible system reference (SYSREF) pulses
- 25 ps analog, and ½ VCO cycle digital delay independently programmable on each of 14 clock output channels
- SPI-programmable phase noise vs. power consumption
- SYSREF valid interrupt to simplify JESD204B/JESD204C synchronization
- Narrow-band, dual core VCOs
- Up to 2 buffered voltage controlled oscillator (VCXO) outputs
- Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes
- Frequency holdover mode to maintain output frequency
- Loss of signal (LOS) detection and hitless reference switching
- 4× GPIOs alarms/status indicators to determine the health of the system
- External VCO input to support up to 6000 MHz
- On-board regulators for excellent PSRR
- 68-lead, 10 mm × 10 mm LFCSP package
The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B/JESD204C type) interfaces. The HMC7044 features two integer mode PLLs and overlapping on-chip VCOs that are SPI-selectable with wide tuning ranges around 2.5 GHz and 3 GHz, respectively. The device is designed to meet the requirements of GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The HMC7044 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays (FPGAs), and mixer local oscillators (LOs).
The DCLK and SYSREF clock outputs of the HMC7044 can be configured to support signaling standards, such as CML, LVDS, LVPECL, and LVCMOS, and different bias settings to offset varying board insertion losses.
- JESD204B/JESD204C clock generation
- Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
- Data converter clocking
- Microwave baseband cards
- Phase array reference distribution
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
The HMC7044 meets the requirements of multi-carrier GSM and LTE base-station designs and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The high performance dual-loop core of the HMC7044 enables the base station designer to attenuate the incoming jitter of a primary system reference clock, such as a CPRI source, with the help of the narrow-band configured first PLL loop, which disciplines an external VCXO, and generate the low phase noise, high frequency clocks with the wider-band second PLL to drive data converter sample clock inputs.
The EK1HMC7044LP10B evaluation board is a compact, easy-to-use platform for evaluating all the features of the HMC7044. A 122.88 MHz VCXO is mounted on the evaluation board to provide a complete solution. All inputs and outputs are configured as differential on the evaluation board.
Full specifications on the HMC7044 are available in the product data sheet, which should be consulted in conjunction with this user guide when working with the evaluation board.
Features & Benefits
- Simple power connection using USB connection and on-board LDO voltage regulators
- LDOs can be bypassed for power measurements
- AC-coupled differential SMA connectors
- SMA connectors for
2 reference Inputs
6 clock outputs
1 VCXO output
- Microsoft Windows®–based evaluation software with simple graphical user interface
- On-board PLL loop filter
- Easy access to digital input/output and diagnostic signals via input/output header (4 GPIOs)
- Status LEDs for diagnostic signals
- USB computer interface
Tools & Simulations
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Product Selection Guide (1)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.