ADIsimCLKTM is a clock design tool for predicting phase noise and jitter for Analog Devices' ultralow jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE, or another area demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate, and optimize your design. ADIsimCLK Version 1.7 expands on previous versions with an added model of the AD9528 low jitter clock generator.

Download ADIsimCLK

ADIsimCLK Version 1.7 (released January 2020). Once the zip file has been stored locally, it can be extracted and run by clicking on "setup.exe." Please note: any old versions should be uninstalled before installing the latest version.

View ADIsimCLK Reference Design Files

Key Features

  • Models PLL frequency synthesizers with either external VCOs or integrated PLL/VCOs
  • Analyzes phase noise and jitter including reference, VCO, loop filter, and phase detector contributions
  • Performs nonlinear transient analysis for accurate determination of lock time

The ADIsimCLK clock design tool wizard enables the designer to observe detailed performance data for a simulated clock distribution design within minutes. Optimization of the clock circuit can be accomplished in this interactive environment with spreadsheet-like simplicity and interactivity.

Detailed device models allow analysis of jitter performance (broadband and SONET specifications), phase noise performance, phase noise impact (ACI/ACR, EVM, phase jitter, etc.), jitter impact on ADC performance (SNR, ENOB), and accurate timing analysis (logic analyzer display).