Features and Benefits
- JEDEC JESD204B/JESD204C support
- Low additive jitter: <15 fs rms at 2457.6 MHz (12 kHz to 20 MHz)
- Very low noise floor: −155.2 dBc/Hz at 983.04 MHz
- Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
- Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency of 3200 MHz
- JESD204B/JESD204C-compatible system reference (SYSREF) pulses
- 25 ps analog and ½ clock input cycle digital delay independently programmable on each of 14 clock output channels
- SPI-programmable adjustable noise floor vs. power consumption
- SYSREF valid interrupt to simplify JESD204B/JESD204C synchronization
- Supports deterministic synchronization of multiple HMC7043 devices
- RFSYNC pin or SPI-controlled SYNC trigger for output synchronization of JESD204B/JESD204C
- GPIO alarm/status indicator to determine the health of the system
- Clock input to support up to 6 GHz
- On-board regulator for excellent PSRR
- 48-lead, 7 mm × 7 mm LFCSP package
The HMC7043 is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs.
The HMC7043 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components in a base transceiver station (BTS) system, such as data converters, local oscillators, transmit/receive modules, field programmable gate arrays (FPGAs), and digital front-end ASICs. The HMC7043 can generate up to seven DCLK and SYSREF clock pairs per the JESD204B/JESD204C interface requirements.
The system designer can generate a lower number of DCLK and SYSREF pairs, and configure the remaining output signal paths for independent phase and frequency. Both the DCLK and SYSREF clock outputs can be configured to support different signaling standards, including CML, LVDS, LVPECL, and LVCMOS, and different bias conditions to adjust for varying board insertion losses.
One of the unique features of the HMC7043 is the independent flexible phase management of each of the 14 channels. All 14 channels feature both frequency and phase adjustment. The outputs can also be programmed for 50 Ω or 100 Ω internal and external termination options.
The HMC7043 device features an RF SYNC feature that synchronizes multiple HMC7043 devices deterministically, that is, ensures that all clock outputs start with the same edge. This operation is achieved by rephrasing the nested HMC7043 or SYSREF control unit/divider, deterministically, and then restarting the output dividers with this new phase.
The HMC7043 is offered in a 48-lead, 7 mm × 7 mm LFCSP package with an exposed pad connected to ground.
- JESD204B/JESD204C clock generation
- Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
- Data converter clocking
- Phase array reference distribution
- Microwave baseband cards
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (2)
The HMC7043 is a high performance clock buffer for the distribution of ultralow phase noise references for high speed data converters with either parallel or serial (JESD204B/JESD204C type) interfaces. The HMC7043 is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs.
The EK1HMC7043LP7F evaluation kit is a compact, easy-to-use platform for evaluating all the features of the HMC7043. All inputs and outputs are configured as differential on the EV2HMC7043LP7F evaluation board.
Full specifications on the HMC7043 are available in the product data sheet, which should be consulted in conjunction with this user guide UG-826 when working with the evaluation board.
Features & Benefits
- Simple power connection using USB connection and on-board low dropout (LDO) voltage regulator
- LDO can be bypassed for power measurements
- AC-coupled differential SMA connectors
- SMA connectors for
1 clock input
1 RF sync input
6 clock outputs
- Microsoft® Windows®–based evaluation software with simple graphical user interface (GUI)
- Easy access to digital input/output and diagnostic signals via input/output header (GPIO)
- Status LED for diagnostic signals
- USB computer interface
The Quad-MxFE System Development Platform contains four MxFE® software defined, direct RF sampling transceivers, as well as associated RF front-ends, clocking, and power circuitry. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a 16 transmit/16 receive channel direct sampling phased array at L/S/C band (0.1 GHz to ~5GHz). The Rx & Tx RF front-end has drop-in configurations that allow for customized frequency ranges, depending on the user’s application.
The Quad-MxFE System Development Platform highlights a complete system solution. It is intended as a testbed for demonstrating multi-chip synchronization as well as the implementation of system level calibrations, beamforming algorithms, and other signal processing algorithms. The system is designed to mate with a VCU118 Evaluation Board from Xilinx®, which features the Virtex® UltraScale+™ XCVU9P FPGA, with provided reference software, HDL code, and MATLAB system-level interfacing.
In addition to the Quad-MxFE Digitizing Card, the kit also contains a 16Tx / 16Rx Calibration Board that is used to develop system-level calibration algorithms, or otherwise more easily demonstrate power-up phase determinism in situations pertinent to their own use case. The Calibration Board also allows the user to demonstrate combined-channel dynamic range, spurious, and phase noise improvements and can also be controlled via a free MATLAB add-on when connected to the PMOD interface of the VCU118.
The system can be used to enable quick time-to-market development programs for applications like:
- ADEF (Phased-Array, RADAR, EW, SATCOM)
- Communications Infrastructure (Multiband 5G and mmWave 5G)
- Electronic Test and Measurement
Features & BenefitsQuad-MxFE Digitizing Card
- Multi-Channel, Wideband System Development Platform Using MxFE
- Mates With Xilinx VCU118 Evaluation Board (Not Included)
- 16x RF Receive (Rx) Channels (32x Digital Rx Channels)
- Total 16x 1.5GSPS to 4GSPS ADC
- 48x Digital Down Converters (DDCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
- 16x Programmable Finite Impulse Response Filters (pFIRs)
- 16x RF Transmit (Tx) Channels (32x Digital Tx Channels)
- Total 16x 3GSPS to 12GSPS DAC
- 48x Digital Up Converters (DUCs) , Each Including Complex Numerically-Controlled Oscillators (NCOs)
- Flexible Rx & Tx RF Front-Ends
- Rx: Filtering, Amplification, Digital Step Attenuation for Gain Control
- Tx: Filtering, Amplification
- On-Board Power Regulation from Single 12V Power Adapter (Included)
- Flexible Clock Distribution
- On-Board Clock Distribution from Single External 500MHz Reference
- Support for External Converter Clock per MxFE
- Mates to Quad-MxFE Digitizing Card & VCU118 PMOD Interface (Cable Included)
- Provides Both Individual Adjacent Channel Loopback and Combined Channel Loopback Options
- Combined Tx Channels Out Via SMA Option
- Combined Rx Channels In Via SMA Option
- On-Board Log Power Detectors With AD5592R Output To VCU118 Over PMOD
- On-Board Power Regulation from Single 12V Power Adapter (Included)
Easy Control Tools and Platform Interfaces to Simplify Software Framework Developments:
- IIO Oscilloscope GUI
- MATLAB Add-Ons & Example Scripts
- Example HDL Builds including JESD204b/JESD204c Bring-Up
- Embedded Software Solutions for Linux and Device Drivers
- MATLAB System Applications GUI
- Multi-Chip Synchronization for Power-Up Phase Determinism
- System-Level Amplitude/Phase Alignment Using NCOs
- Low-Latency ADC-to-DAC Loopback Bypassing JESD Interface
- pFIR Control for Broadband Channel-to-Channel Amplitude/Phase Alignment
- Fast-Frequency Hopping
- Calibration Board MATLAB Driver File
- FPGA Programming MATLAB Script
Documentation & Resources
Clock Skew in Large Multi-GHz Clock Trees1/1/2019 Analog Dialogue
Synchronizing Sample Clocks of a Data Converter Array6/1/2016
Tools & Simulations
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Support & Discussions
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.