LTC6957
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LTC6957

Low Phase Noise, Dual Output Buffer/Driver/Logic Converter

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Part Details
Part Models 22
1ku List Price Starting From $4.50
Features
  • Low Phase Noise Buffer/Driver
  • Optimized Conversion of Sine Wave Signals to Logic Levels
  • Three Logic Output Types Available
    • LVPECL
    • LVDS
    • CMOS
  • Additive Jitter 45fsRMS (LTC6957-1)
  • Frequency Range Up to 300MHz
  • 3.15V to 3.45V Supply Operation
  • Low Skew 3ps Typical
  • Fully Specified from –40°C to 125°C
  • 12-Lead MSOP and 3mm × 3mm DFN Packages
Additional Details
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The LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 is a family of very low phase noise, dual output AC signal buffer/driver/logic level translators. The input signal can be a sine wave or any logic level (≤2VP-P). There are four members of the family that differ in their output logic signal type as follows:

LTC6957-1: LVPECL Logic Outputs

LTC6957-2: LVDS Logic Outputs

LTC6957-3: CMOS Logic, In-Phase Outputs

LTC6957-4: CMOS Logic, Complementary Outputs

The LTC6957 will buffer and distribute any logic signal with minimal additive noise, however, the part really excels at translating sine wave signals to logic levels. The early amplifier stages have selectable lowpass filtering to minimize the noise while still amplifying the signal to increase its slew rate. This input stage filtering/noise limiting is especially helpful in delivering the lowest possible phase noise signal with slow slewing input signals such as a typical 10MHz sine wave system reference.

Applications

  • System Reference Frequency Distribution
  • High Speed ADC, DAC, DDS Clock Driver
  • Military and Secure Radio
  • Low Noise Timing Trigger
  • Broadband Wireless Transceiver
  • High Speed Data Acquisition
  • Medical Imaging
  • Test and Measurement
Part Models 22
1ku List Price Starting From $4.50

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
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Feb 4, 2020

- 20_0129

Laser Mark Conversion for 12-Lead MSOP Packages Assembled in ADPG and UTAC

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Mar 20, 2024

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Feb 4, 2020

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Laser Mark Conversion for 12-Lead MSOP Packages Assembled in ADPG and UTAC

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Mar 20, 2024

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Obsolescence of Tower Fab3 (JAZZ-3) SBC35 Process

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Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 5

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DC1765A-B

LTC6957HMS-2 Demo Board | Low Phase Noise, Dual Output Buffer/Driver/Logic Converter with LVDS Outputs

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DC1766A-B

LTC6957HMS-4 Demo Board | Low Phase Noise, Dual Output Buffer/Driver/Logic Converter with Complementary CMOS Outputs

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DC1766A-B

LTC6957HMS-4 Demo Board | Low Phase Noise, Dual Output Buffer/Driver/Logic Converter with Complementary CMOS Outputs

LTC6957HMS-4 Demo Board | Low Phase Noise, Dual Output Buffer/Driver/Logic Converter with Complementary CMOS Outputs

Product Detail

DC1766A-B: Demo Board for the LTC6957 Low Phase Noise, Dual Output Buffer/Driver/Logic Converter.

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DC1765A-A

LTC6957HMS-1 Demo Board | Low Phase Noise, Dual Output Buffer/Driver/Logic Converter with LVPECL Outputs

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DC1766A-A

LTC6957HMS-3 Demo Board | Low Phase Noise, Dual Output Buffer/Driver/Logic Converter with In-Phase CMOS Outputs

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DC1766A-A

LTC6957HMS-3 Demo Board | Low Phase Noise, Dual Output Buffer/Driver/Logic Converter with In-Phase CMOS Outputs

LTC6957HMS-3 Demo Board | Low Phase Noise, Dual Output Buffer/Driver/Logic Converter with In-Phase CMOS Outputs

Product Detail

DC1766A-A: Demo Board for the LTC6957 Low Phase Noise, Dual Output Buffer/Driver/Logic Converter.

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AD-SYNCHRONA14-EBZ

Multichannel System Clocking Device

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AD-SYNCHRONA14-EBZ

Multichannel System Clocking Device

Multichannel System Clocking Device

Features and Benefits

Processing System

  • Raspberry Pi 4, ARM Cortex-A72, 2GB SDRAM

User Interfaces

  • Gigabit Ethernet
  • 2 × USB 3.0 ports
  • 2 × USB 2.0 ports
  • SPI interface
  • GPIO
  • 2 bicolor LEDs
  • Male pin header

Clock Processing Devices

  • HMC7044 (High Performance, 3.2 GHz, 14-Output Jitter Attenuator)
  • AD9545 (1 PPS Synchronizer and Adaptive Clock Translator)

Clock Outputs

  • 4 x TWINAX LVPECL AC&DC coupled, 100Ω diff
  • 2 x SMA LVPECL AC coupled*
  • 4 x SMA CMOS*
  • 4 x SMA LVDS AC coupled*

*Configurable differential outputs, 50Ω diff

Clock Inputs

  • 3 differential 100Ω SMA clock inputs
  • PPS input
  • SYNC input
  • 10MHz input

Internal references

  • 100Mhz and 122.88Mhz Ultra-Low Phase Noise VCXO's (-165dBc/Hz)
  • 40Mhz and 38.4Mhz TCXO's (±1ppm) 50MHz OCXO(+/- 10ppb)
  • Internal references are software configurable

Power supply

  • DC 12V, 3A barrel jack

Product Detail

The AD-SYNCHRONA14-EBZ is an ideal self-contained device to use in evaluation and prototyping of applications that need a highly accurate frequency and phase-controlled source clock. It is designed around the Analog Devices AD9545 and HMC7044 and greatly simplifies clock distribution and multi-channel synchronization in complex systems. It is intended to be used by trained professionals in a laboratory environment, and not intended as an end product for commercial use. It can be taken as a complete reference design and customised as required for any end customer applications. Full design details are made available free of charge.

The AD-SYNCHRONA14-EBZ comes in a 1U mechanical form factor. Using popular industry connector SMA and TwinAX interfaces most labs will already have the needed cables.

With its internal OCXO it can operate in standalone mode or be fed from a choice of external sources, such as 3 separate high speed differential clock inputs, a 10MHz reference and 1PPS. This flexibility combined with the capability to select either of the internal VCXO options of 100MHz or 122.88MHz, gives almost unlimited choice for the frequency of interest and accuracy needed for a wide variety of application areas. 

APPLICATIONS

  • High accuracy reference clock distribution
  • Systems clocked from a single source
  • Clocks derived from 100MHz or 122.88MHz
  • Phased Array Systems, RADAR, EW, SATCOMS, SDR
  • Bench Equipment
  • Remote controlled operation

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