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Features
- 95 ps propagation delay
- 7.5 GHz toggle rate
- 60 ps typical output rise/fall
- 60 fs random jitter (RJ)
- On-chip terminations at both input pins
- Extended industrial temperature range: −40°C to +125°C
- 2.5 V to 3.3 V power supply (VCC − VEE)
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The ADCLK905 (one input, one output), ADCLK907 (dual one input, one output), and ADCLK925 (one input, two outputs) are ultrafast clock/data buffers fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process.
The ADCLK905/ADCLK907/ADCLK925 feature full-swing emitter coupled logic (ECL) output drivers. For PECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply.
The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate, 10 Gbps data rate, and 60 fs random jitter (RJ).
The inputs have center tapped, 100 Ω, on-chip termination resistors. A VREF pin is available for biasing ac-coupled inputs.
The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differential output swing of 1.6 V.
The ADCLK905/ADCLK907/ADCLK925 are available in 16-lead LFCSP packages.
Applications
- Clock and data signal restoration and level shifting
- Automated test equipment (ATE)
- High speed instrumentation
- High speed line receivers
- Threshold detection
- Converter clocking
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ADCLK905
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Application Note 9
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev.0)
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev.0)
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev.0)
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev.0)
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev.0)
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev.0)
AN-741: Little Known Characteristics of Phase Noise (Rev.0)
AN-501: Aperture Uncertainty and ADC System Performance (Rev.A)
AN-769: Generating Multiple Clock Outputs from the AD9540
Technical Articles 3
Frequently Asked Question 1
Tutorial 1
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Product Selection Guide 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| ADCLK905BCPZ-R2 |
16-Lead LFCSP (3mm x 3mm w/ EP)
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| ADCLK905BCPZ-R7 |
16-Lead LFCSP (3mm x 3mm w/ EP)
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| ADCLK905BCPZ-WP |
16-Lead LFCSP (3mm x 3mm w/ EP)
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- ADCLK905BCPZ-R2
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16-Lead LFCSP (3mm x 3mm w/ EP)
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SamacSys
- ADCLK905BCPZ-R7
- Pin/Package Drawing
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16-Lead LFCSP (3mm x 3mm w/ EP)
- Documentation
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HTML
Material Declaration
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HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
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Ultra Librarian
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SamacSys
- ADCLK905BCPZ-WP
- Pin/Package Drawing
-
16-Lead LFCSP (3mm x 3mm w/ EP)
- Documentation
-
HTML
Material Declaration
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HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
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Ultra Librarian
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SamacSys
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PCN
Feb 13, 2014
- 14_0038
Conversion of 3x3mm body Size LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to Amkor Philippines.
ADCLK905BCPZ-R2
ADCLK905BCPZ-R7
PRODUCTION
Filter by Model
Part Models
Product Lifecycle
PCN
Feb 13, 2014
- 14_0038
Conversion of 3x3mm body Size LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to Amkor Philippines.
ADCLK905BCPZ-R2
ADCLK905BCPZ-R7
PRODUCTION
Software & Part Ecosystem
Evaluation Kits 1
EVAL-ADCLK905
ADCLK905 Evaluation Board
Product Detail
The ADCLK905/ADCLK907/ADCLK925 clock buffers are very fast, making it important to use adequate high bandwidth instruments to evaluate them. To that end, the evaluation board is fabricated using a high quality dielectric material between layers to maintain high signal integrity. Transmission line paths are kept as close to 50 Ω as possible.
Resources
Evaluation Kits1
Tools & Simulations 2
IBIS Model 1
IBIS Model
ADIsimCLK Design and Evaluation Software
Reference Designs 1
CN0290
Extending the Low Frequency Range of a High Performance Phase Locked Loop
Circuits from the lab
Info:Circuits from the lab
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