ADF4106

PRODUCTION

ADF4106

6 GHz integer-N PLL

PRODUCTION

PRODUCTION

Part Details

ADF4106 Functional Block Diagram slide

ADF4106 Pin Configuration slide

ADF4106 Pin Configuration slide

ADF4106 Functional Block Diagram

ADF4106 Pin Configuration

ADF4106 Pin Configuration

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Features

6.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems
Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode

ADF4106-EP supports defense and aerospace applications (AQEC standard)

Download ADF4106-EP data sheet (pdf)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available upon request
V62/11606 DSCC Drawing Number

Additional Details

The ADF4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A counter and B counter, and a dual-modulus prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.

ADF4106-EP Supports defense and aerospace applications (AQEC standard).

Applications

Broadband wireless access
Satellite systems
Instrumentation
Wireless LANS
Base stations for wireless radios

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Ask a Question

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Support

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FAQs

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Documentation

Technical Documents 13

ADF4106: PLL Frequency Synthesizer Data Sheet (Rev.E) 09/30/2015

ADF4106-EP: Enhanced Product Data Sheet (Rev.D) 09/30/2015

ADF4106-DSCC: Military Data Sheet 09/30/2015

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UG-161: PLL Frequency Synthesizer Evaluation Board 09/14/2015

UG-159: LMDS Evaluation Board for PLL Frequency Synthesizer 10/06/2015

UG-582: Evaluating the EVAL-CN0290-SDPZ 09/04/2013

UG-476: PLL Software Installation Guide 08/10/2015

Show More

AN-807: Multicarrier WCDMA Feasibility (Rev.0) 11/09/2007

AN-808: Multicarrier CDMA2000 Feasibility (Rev.0) 11/09/2007

AN-30: Ask the Applications Engineer - PLL Synthesizers 12/06/2004

AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev.0) 12/06/2006

AN-1039: Correcting Imperfections in IQ Modulators to Improve RF Signal Fidelity 07/12/2024

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Reference Materials 16

CN-0290: Extending the Low Frequency Range of a High Performance Phase Locked Loop 09/24/2013

ADF4106 GitHub no-OS Driver Source Code 07/29/2024

RF, Microwave, and Millimeter Wave Product Selection Guide 07/13/2018

How to Design and Debug a Phase-Locked Loop (PLL) Circuit 09/01/2013

Direct Digital Synthesis (DDS) Controls Waveforms in Test, Measurement, and Communications 08/01/2005

Phase-Locked Loops for High-Frequency Receivers and Transmitters - Part 3 07/01/1999

Fast-Locking, High Sensitivity Tuned-IF Radio Receiver Achieved with a 7-GHz Synthesizer 05/01/2003

Design a Direct 6-GHz Local Oscillator with a New, Wideband, Integer-N, PLL Synthesizer 11/01/2001

Ask the Applications Engineer—30: PLL Synthesizers 05/01/2002

Phase-Locked Loops for High-Frequency Receivers and Transmitters - Part 2 05/01/1999

Phase-Locked Loops for High-Frequency Receivers and Transmitters - Part 1 03/01/1999

Fundamentals of Frequency Synthesis, Part 1: Phased Locked Loops 04/10/2017

Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS) 04/10/2017

Fundamentals of Clocks 03/06/2017

Latest Developments in Analog Devices PLL Portfolio 02/01/2018

Video

1

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Video

2017-06-30

03:02

High Integration SiGe Solutions for Freq. Generation & Conversion

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Software & Part Ecosystem

Software 3

ADF4106 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design

BeMicro FPGA Project for ADF4106 with Nios driver

ADF4106 GitHub no-OS Driver Source Code NEW

View Evaluation Software

external link

Companion Parts 10

Parts	Product Life Cycle	Description
Frequency Dividers, Prescalers, and Counters1
ADF5001	PRODUCTION	4 GHz TO 18 GHz Divide-by-4 Prescaler
I/Q Demodulators1
ADL5380	RECOMMENDED FOR NEW DESIGNS	400 MHz TO 6000 MHz Quadrature Demodulator
I/Q Modulators1
ADL5375	PRODUCTION	400 MHz TO 6 GHz Broadband Quadrature Modulator
Internal Power Switch Boost Regulators1
ADP1613	PRODUCTION	650 kHz /1.3 MHz Step-Up PWM DC-to-DC Switching Converter with 2.0 A Current Limit
Positive Linear Regulators (LDO)3
ADP150	PRODUCTION	Ultralow Noise, 150 mA CMOS Linear Regulator
ADP151	PRODUCTION	Ultralow Noise, 200 mA, CMOS Linear Regulator
ADP3334	NOT RECOMMENDED FOR NEW DESIGNS	High Accuracy Low I_Q, 500 mA anyCAP^® Adjustable Low Dropout Regulator
Precision Op Amps (Vos ≤1mV & TCVos ≤2uV/C)1
OP184	PRODUCTION	Single-Supply Rail-to-Rail Input/Output Operational Amplifier
Single, Double, and Triple Balanced Mixers2
ADL5801	RECOMMENDED FOR NEW DESIGNS	High IP3, 10 MHz TO 6 GHz, Active Mixer
ADL5802	RECOMMENDED FOR NEW DESIGNS	Dual Channel High IP3 100 MHz TO 6 GHz Active Mixer

Evaluation Kit

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EVAL-ADF4106

ADF4106 Evaluation Board

ADF4106 Evaluation Board

ADF4106 Evaluation Board - Top View

ADF4106 Evaluation Board - Bottom View

ADF4106 Evaluation Board

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ADF4106 Evaluation Board

ADF4106 Evaluation Board - Top View

ADF4106 Evaluation Board - Bottom View

ADF4106 Evaluation Board

ADF4106 Evaluation Board - Top View

ADF4106 Evaluation Board - Bottom View

EVAL-ADF4106

ADF4106 Evaluation Board

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Product Detail

This page contains ordering information for the evaluation board used to evaluate the ADF4106 PLL.

This evaluation board requires an SDP Controller board for connection to the PC. The SDP controller board connects to the PC via USB 2.0. The evaluation board will connect to the SDP controller board. The evaluation board cannot be connected directly to the PC. The evaluation software running on the PC will communicate through the SDP Controller board, to the evaluation board. The SDP Controller board is a separate list item in the ordering guide below (EVAL-SDP-CS1Z). If you have not previously purchased an SDP Controller board, please do so to ensure a full evaluation setup.

Resources

pdf

UG-161: PLL Frequency Synthesizer Evaluation Board

238 kB

pdf

UG-159: LMDS Evaluation Board for PLL Frequency Synthesizer

231 kB

ZIP

ADF4106 Design Files

770.01 K

PDF

UG-476: PLL Software Installation Guide

421.58 K

pdf

UG-476: PLL Software Installation Guide

520 kB

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Software

ZIP

Integer-N Software

12155 kB

evaluation kit item images

EVAL-ADF4106

ADF4106 Evaluation Board

Tools & Simulations

LTspice

LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.

ADIsimPLL™

ADIsimPLL™

ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.

ADIsimRF

ADIsimRF

ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.

IBIS Model 2

Simulation Model

IBIS Model

ADF4106BCPZ IBIS Model

41.15 KB

IBIS Model

ADF4106BRUZ IBIS Model

40.9 KB

Reference Designs

Block Diagram of the EVAL-CN0290-SDPZ

CN0290

Extending the Low Frequency Range of a High Performance Phase Locked Loop

Block Diagram of the EVAL-CN0290-SDPZ

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Extending the Low Frequency Range of a High Performance Phase Locked Loop

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Block Diagram of the EVAL-CN0290-SDPZ

Block Diagram of the EVAL-CN0290-SDPZ

CN0290

Circuits from the lab

Extending the Low Frequency Range of a High Performance Phase Locked Loop

Features and Benefits

Phase locked loop with extended low frequency range
LO down to 10MHz, RF down to 100MHz
Low distortion and phase noise

View Detailed Reference Design

Part Used 5

ADCLK905

ADCLK925

ADF4106

ADP150

ADP7102

Resources

WIKI

ADP150 Regulator Fixed Voltage Linux Driver

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Design & Integration Tools

zip

CN0290 Design & Integration Files

1507 kB

Block Diagram of the EVAL-CN0290-SDPZ

CN0290

Extending the Low Frequency Range of a High Performance Phase Locked Loop

Latest Discussions

40 Weeks Ago

RE: How to use FPGA control ADF4106 realize that the register input values of the ADF4106 can be set and transformed according to the frequency of the FPGA

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Tools & Simulations

Reference Designs

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