Features and Benefits
- Low Phase Noise and Jitter
- Additive Jitter: 18fsRMS (12kHz to 20MHz)
- Additive Jitter: 85fsRMS (10Hz to Nyquist)
- EZSync™ Multichip Clock Edge Synchronization
- Full PLL Core with Lock Indicator
- –226dBc/Hz Normalized In-Band Phase Noise Floor
- –274dBc/Hz Normalized 1/f Phase Noise
- 1.4GHz Maximum VCO Input Frequency
- Four Independent, Low Noise 1.4GHz LVPECL Outputs
- One LVDS/CMOS Configurable Output
- Five Independently Programmable Dividers Covering All Integers from 1 to 63
- Five Independently Programmable VCO Clock Cycle Delays Covering All Integers from 0 to 63
- –40°C to 105°C Junction Temperature Range
The LTC6950 is a low phase noise integer-N frequency synthesizer core with clock distribution. The LTC6950 delivers the low phase noise clock signals demanded in high frequency, high resolution data acquisition systems.
The frequency synthesizer contains a full low noise PLL core with a programmable reference divider (R), a programmable feedback divider (N), a phase/frequency detector (PFD) and a low noise charge pump (CP). The clock distribution section of the LTC6950 delivers up to five outputs based on the VCO input. Each output is individually programmed to divide the VCO input frequency by any integer from 1 to 63 and to delay the output by 0 to 63 VCO clock cycles. Four of the outputs feature very low noise, low skew LVPECL logic signals capable of operation up to 1.4GHz. The fifth output is selectable as either an LVDS (800MHz) or CMOS (250MHz) logic type. This output is also programmed to produce an output signal based on either the VCO input or the reference divider output.
- Clocking High Speed, High Resolution ADCs, DACs and Data Acquisition Systems
- Low Jitter Clock Generation and Distribution
Markets and Technologies
Product Lifecycle Production
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Evaluation Kits (1)
Demonstration circuit 1795A features the LTC6950, a 1.4GHz low phase noise, low jitter PLL with clock distribution. For ease of use, the DC1795A comes installed with a 100MHz reference and a 1GHz VCSO, voltage controlled SAW oscillator with sine wave output. All differential inputs and outputs have 0.5" spaced SMA connectors. The DC1795A has four AC coupled LVPECL outputs with 50Ω transmission lines making them suitable to drive 50Ω impedance instruments. The LVDS/CMOS output is DC coupled. The LTC6950’s EZSync™ function is made available via a turret and an SMA connector.
Software & Systems Requirements
Tools & Simulations
Linduino is Analog Devices’ Arduino compatible system for developing and distributing firmware libraries and example code for our integrated circuits. Each Linduino-supported product includes an example main program, defined in the LTSketchbook/Part Number folder and driver code, defined in the LTSketchbook/libraries folder.
Solutions Bulletins & Brochures (1)
Press Releases (1)
Technical Articles (2)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.