LTC6950
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LTC6950

1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution

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Part Details
Part Models 1
1ku List Price
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Features
  • Low Phase Noise and Jitter
  • Additive Jitter: 18fsRMS (12kHz to 20MHz)
  • Additive Jitter: 85fsRMS (10Hz to Nyquist)
  • EZSync Multichip Clock Edge Synchronization
  • Full PLL Core with Lock Indicator
  • –226dBc/Hz Normalized In-Band Phase Noise Floor
  • –274dBc/Hz Normalized 1/f Phase Noise
  • 1.4GHz Maximum VCO Input Frequency
  • Four Independent, Low Noise 1.4GHz LVPECL Outputs
  • One LVDS/CMOS Configurable Output
  • Five Independently Programmable Dividers Covering All Integers from 1 to 63
  • Five Independently Programmable VCO Clock Cycle Delays Covering All Integers from 0 to 63
  • –40°C to 105°C Junction Temperature Range
Additional Details
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The LTC6950 is a low phase noise integer-N frequency synthesizer core with clock distribution. The LTC6950 delivers the low phase noise clock signals demanded in high frequency, high resolution data acquisition systems.

The frequency synthesizer contains a full low noise PLL core with a programmable reference divider (R), a programmable feedback divider (N), a phase/frequency detector (PFD) and a low noise charge pump (CP). The clock distribution section of the LTC6950 delivers up to five outputs based on the VCO input. Each output is individually programmed to divide the VCO input frequency by any integer from 1 to 63 and to delay the output by 0 to 63 VCO clock cycles. Four of the outputs feature very low noise, low skew LVPECL logic signals capable of operation up to 1.4GHz. The fifth output is selectable as either an LVDS (800MHz) or CMOS (250MHz) logic type. This output is also programmed to produce an output signal based on either the VCO input or the reference divider output.

Applications

  • Clocking High Speed, High Resolution ADCs, DACs and Data Acquisition Systems
  • Low Jitter Clock Generation and Distribution
Part Models 1
1ku List Price
price unavailable

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
LTC6950IUHH#TRPBF
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Software & Part Ecosystem

Software & Part Ecosystem

 

ClockWizard

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ClockWizard builds on PLLWizard and simplifies the evaluation process of the LTC6950. Besides the ability to design the loop filter components and predict the resulting phase noise and jitter performance, ClockWizard introduces a scope plot which shows the LTC6950 outputs in the time domain and illustrates the phase relationships between the outputs based on their respective EZSync settings. It also controls the LTC6950 demoboard via the DC590 or DC2026.

Evaluation Kit

Evaluation Kits 1

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DC1795A

LTC6950 Demo Board | Integer-N PLL with 5 Outputs (Requires DC590 or DC2026)

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DC1795A

LTC6950 Demo Board | Integer-N PLL with 5 Outputs (Requires DC590 or DC2026)

LTC6950 Demo Board | Integer-N PLL with 5 Outputs (Requires DC590 or DC2026)

Product Detail

Demonstration circuit 1795A features the LTC6950, a 1.4GHz low phase noise, low jitter PLL with clock distribution. For ease of use, the DC1795A comes installed with a 100MHz reference and a 1GHz VCSO, voltage controlled SAW oscillator with sine wave output. All differential inputs and outputs have 0.5" spaced SMA connectors. The DC1795A has four AC coupled LVPECL outputs with 50Ω transmission lines making them suitable to drive 50Ω impedance instruments. The LVDS/CMOS output is DC coupled. The LTC6950’s EZSync™ function is made available via a turret and an SMA connector.

Tools & Simulations

Tools & Simulations 2

Linduino

Linduino is Analog Devices’ Arduino compatible system for developing and distributing firmware libraries and example code for our integrated circuits. Each Linduino-supported product includes an example main program, defined in the LTSketchbook/Part Number folder and driver code, defined in the LTSketchbook/libraries folder.

Linduino code repository on GitHub and instructions on how to use the code.

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