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AD9511
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
Overview
Features and Benefits
- Low phase noise phase-locked loop core
- Reference input frequencies to 250 MHz
- Programmable dual-modulus prescaler
- Programmable charge pump (CP) current
- Separate CP supply (VCP) extends tuning range
- Two 1.6 GHz, differential clock inputs
- 5 programmable dividers, 1 to 32, all integers
- Phase select for output-to-output coarse delay adjust
- 3 independent 1.2 GHz LVPECL outputs
- Additive output jitter , 225 fs RMS
- 2 independent 800 MHz/250 MHz LVDS/CMOS outputs
- Additive output jitter, 275 fs RMS
- Fine delay adjust on one output, 5-bit delay words
- Serial control port
- Space-saving 48-lead LFCSP
Product Details
The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.
The PLL section consists of a programmable reference divider (R); a low noise phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.6 GHz may be synchronized to the input reference.
There are five independent clock outputs. Three outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels.
Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. One of the LVDS/CMOS outputs features a programmable delay element with full-scale ranges up to 10 ns of delay. This fine tuning delay block has 5-bit resolution, giving 32 possible delays from which to choose for each full-scale setting.
The AD9511 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.
The AD9511 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is −40°C to +85°C.
APPLICATIONS
- Low jitter, low phase noise clock distribution
- Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFEs
- High performance wireless transceivers
- High performance instrumentation
- Broadband infrastructure
Product Categories
Markets and Technologies
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
Documentation
Application Notes (10)
Demo Board Schematic (1)
Frequently Asked Questions (1)
Tools & Simulations
Design Tools
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Reference Materials
Product Selection Guide (1)
Circuit Note (1)
Technical Articles (7)
Press Releases (1)
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
PCN-PDN Information
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AD9511 Discussions
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