AD9680
RECOMMENDED FOR NEW DESIGNS14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter
- Part Models
- 8
- 1ku List Price
- Starting From $349.25
Part Details
- JESD204B (Subclass 1) coded serial digital outputs
- 1.65 W total power per channel at 1 GSPS (default settings)
- SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz
- SNR at 1 GSPS = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 60.5 dBFS at 1 GHz (AIN = −1.0 dBFS)
- ENOB = 10.8 bits at 10 MHz
- DNL = ±0.5 LSB
- INL = ±2.5 LSB
- Flexible input range: 1.46 Vp-p to 1.94 Vp-p
- AD9680-1250: 1.58 Vp-p nominal
- AD9680-1000 and AD9680-820: 1.70 V p-p nominal
- AD9680-500: 1.46 Vp-p to 2.06 Vp-p (2.06 Vp-p nominal)
- Noise density = −154 dBFS/Hz at 1 GSPS
- 1.25 V, 2.5 V, and 3.3 V dc supply operation
- No missing codes
- Internal ADC voltage reference
- Programmable termination impedance
- 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
- 2 GHz usable analog input full power bandwidth
- 95 dB channel isolation/crosstalk
- Amplitude detect bits for efficient AGC implementation
- 2 integrated wideband digital processors per channel
- 12-bit NCO, up to 4 half-band filters
- Differential clock input
- Integer clock divide by 1, 2, 4, or 8
- Flexible JESD204B lane configurations
- Small signal dither
The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.
In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.
The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.
The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
- Wide full power bandwidth supports IF sampling of signals up to 2 GHz.
- Buffered inputs with programmable input termination eases filter design and implementation.
- Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.
- Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.
- Programmable fast overrange detection.
- 9 mm × 9 mm, 64-lead LFCSP.
APPLICATIONS
- Communications
- Diversity multiband, multimode digital receivers
- 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
- General-purpose software radios
- Ultrawideband satellite receivers
- Instrumentation
- Radars
- Signals intelligence (SIGINT)
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
Documentation
Data Sheet 1
User Guide 1
Application Note 1
Technical Articles 17
Informational 1
Video 1
Device Drivers 3
3rd Party Solutions 1
FPGA Interoperability Reports 2
Rarely Asked Question Page 4
Analog Dialogue 8
Webcast 5
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9680BCPZ-1000 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9680BCPZ-1250 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9680BCPZ-500 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9680BCPZ-820 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9680BCPZRL7-1000 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9680BCPZRL7-1250 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9680BCPZRL7-500 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9680BCPZRL7-820 | 64-Lead LFCSP (9mm x 9mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Dec 9, 2016 - 16_0107 AD9680-500/820/1000/1250 Die Revision and Data Sheet Change |
||
| AD9680BCPZ-1000 | PRODUCTION | |
| AD9680BCPZ-1250 | PRODUCTION | |
| AD9680BCPZ-500 | PRODUCTION | |
| AD9680BCPZ-820 | PRODUCTION | |
| AD9680BCPZRL7-1000 | PRODUCTION | |
| AD9680BCPZRL7-1250 | PRODUCTION | |
| AD9680BCPZRL7-500 | PRODUCTION | |
| AD9680BCPZRL7-820 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 3
Evaluation Software 2
JESD204 Interface Framework
Integrated JESD204 software framework for rapid system-level development and optimization
JESD204x Frame Mapping Table Generator
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
Can't find the software or driver you need?
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 3 | ||
| LTC6955 | LAST TIME BUY | Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
| LTC6953 | LAST TIME BUY | Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support |
| HMC7043 | RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C |
| Clock Generation Devices 4 | ||
| LTC6951 | LAST TIME BUY | Ultralow Jitter Multi-Output Clock Synthesizer with Integrated VCO |
| LTC6952 | LAST TIME BUY | Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
| HMC7044 | RECOMMENDED FOR NEW DESIGNS | High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
| AD9528 | RECOMMENDED FOR NEW DESIGNS | JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs |
| Digital Control VGAs 2 | ||
| ADA4961 | RECOMMENDED FOR NEW DESIGNS | Low Distortion, 3.2 GHz, RF DGA |
| ADL5205 | RECOMMENDED FOR NEW DESIGNS |
Dual, 35 dB Range, 1 dB Step Size DGA |
| Fully Differential Amplifiers 4 | ||
| ADL5565 | RECOMMENDED FOR NEW DESIGNS |
6 GHz Ultrahigh Dynamic Range Differential Amplifier |
| ADL5569 | RECOMMENDED FOR NEW DESIGNS | 6.5 GHz, Ultrahigh Dynamic Range, Differential Amplifier |
| ADL5567 | RECOMMENDED FOR NEW DESIGNS | 4.3 GHz, Ultrahigh Dynamic Range, Dual Differential Amplifier |
| ADL5566 | RECOMMENDED FOR NEW DESIGNS | 4.5 GHz Ultrahigh Dynamic Range, Dual Differential Amplifier |
| Internal Power Switch Buck Regulators 2 | ||
| ADP2164 | RECOMMENDED FOR NEW DESIGNS | 6.5V, 4 A, High Efficiency, Step-Down DC-to-DC Regulator |
| ADP2384 | RECOMMENDED FOR NEW DESIGNS | 20 V, 4 A, Synchronous Step-Down DC-to-DC Regulator |
| Positive Linear Regulators (LDO) 1 | ||
| ADP1741 | PRODUCTION | 2 A, Low VIN, Dropout, CMOS Linear Regulator |
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
Open ToolIBIS Model 1
AD9680 AMI Model
Open ToolDesign Tool 1
Visual Analog
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
Open ToolADIsimRF
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
Open ToolADC Companion Transport Layer RTL Code Generator Tool
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
Open ToolMathWorks® 1
AD9680 MATLAB ADIsimADC
Open ToolS-Parameter 1
LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.
Evaluation Kits
High speed data acquisition FMC board
Resources
Software
AD-FMCDAQ2-EBZ Evaluation Board
Resources
AD9680/AD9234/AD9690 Evaluation Board
Resources
ADA4961 & AD9680 Analog Signal Chain Evaluation and AD9528 Converter Synchronization
Resources
Software
FPGA Based Data Capture Kit