AD9680
14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter
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Overview
Features and Benefits
- JESD204B (Subclass 1) coded serial digital outputs
- 1.65 W total power per channel at 1 GSPS (default settings)
- SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz
- SNR at 1 GSPS = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 60.5 dBFS at 1 GHz (AIN = −1.0 dBFS)
- ENOB = 10.8 bits at 10 MHz
- DNL = ±0.5 LSB
- INL = ±2.5 LSB
- Flexible input range: 1.46 Vp-p to 1.94 Vp-p
- AD9680-1250: 1.58 Vp-p nominal
- AD9680-1000 and AD9680-820: 1.70 V p-p nominal
- AD9680-500: 1.46 Vp-p to 2.06 Vp-p (2.06 Vp-p nominal)
- Noise density = −154 dBFS/Hz at 1 GSPS
- 1.25 V, 2.5 V, and 3.3 V dc supply operation
- No missing codes
- Internal ADC voltage reference
- Programmable termination impedance
- 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
- 2 GHz usable analog input full power bandwidth
- 95 dB channel isolation/crosstalk
- Amplitude detect bits for efficient AGC implementation
- 2 integrated wideband digital processors per channel
- 12-bit NCO, up to 4 half-band filters
- Differential clock input
- Integer clock divide by 1, 2, 4, or 8
- Flexible JESD204B lane configurations
- Small signal dither
Product Details
The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.
In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.
The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.
The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
- Wide full power bandwidth supports IF sampling of signals up to 2 GHz.
- Buffered inputs with programmable input termination eases filter design and implementation.
- Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.
- Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.
- Programmable fast overrange detection.
- 9 mm × 9 mm, 64-lead LFCSP.
APPLICATIONS
- Communications
- Diversity multiband, multimode digital receivers
- 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
- General-purpose software radios
- Ultrawideband satellite receivers
- Instrumentation
- Radars
- Signals intelligence (SIGINT)
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
Product Categories
Markets and Technologies
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (5)
Documentation & Resources
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AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)5/12/2015PDF985 kB
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JESD204B Link Debugging Guidelines2/27/2018
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JESD204 Serial Interface2/14/2015
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Dual Channel 1GSPS Data Acquisition Kit10/15/2018
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Interfacing FPGAs to an ADC’s Digital Data Output11/1/2019
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JESD204B Subclasses—Part 2: Subclass 1 vs. Subclass 2 System Considerations10/1/2019
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JESD204B Subclasses—Part 1: An Introduction to JESD204B Subclasses and Deterministic Latency10/1/2019
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The ABCs of Interleaved ADCs10/1/2019
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New, Faster JESD204B Standard for High Speed Data Converters Comes with Verification Challenges10/1/2019
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Grasp the Critical Issues for a Functioning JESD204B Interface9/1/2019
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Use Noise Spectral Density to Evaluate ADCs in Software-Defined Systems6/1/2017
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A Review of Wideband RF Receiver Architecture Options2/1/2017
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What’s Up With Digital Downconverters—Part 211/1/2016 Analog Dialogue
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Crossing a New Frontier of Multiband Receivers with Gigasample ADCs—Part One8/1/2016 Analog Dialogue
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What’s Up With Digital Downconverters—Part 17/1/2016 Analog Dialogue
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Digital Signal Processing in IF/RF Data Converters4/1/2016
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Powering GSPS or RF Sampling ADCs: Switcher vs. LDO2/1/2016 Analog Dialogue
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Aerospace and Defense Mobilize Insatiable Bandwidth Applications1/1/2016
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An Engineering Walk Through Virtual Eval, ADI's Online Data Converter Product Evaluation Tool1/1/2016 Analog Dialogue
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Powering GSPS or RF Sampling ADCs: Switcher vs. LDO11/1/2015
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Clocking Wideband GSPS JESD204B ADCs8/1/2015
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Not Your Grandfather's ADC: RF Sampling ADCs Offer Advantages in Systems Design7/1/2015
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Interleaving ADCs: Unraveling the Mysteries7/1/2015 Analog Dialogue
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Multifunction: a Dilemma or Reality?6/1/2015 Analog Dialogue
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RF-Sampling ADC Input Protection: Not Black Magic After All4/1/2015 Analog Dialogue
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GSPS Data Converters to the Rescue for Electronics Surveillance and Warfare Systems!12/1/2014
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Maximizing the Dynamic Range of Software-Defined Radio11/1/2014
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Understanding Layers in the JESD204B Specification—A High Speed ADC Perspective10/1/2014
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Understanding Spurious-Free Dynamic Range in Wideband GSPS ADCs8/1/2014
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Presto! Multiply Your ADC’s Virtual Channel Count with DDC Magic4/1/2017
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Because Mr. Ohm Said So …10/1/2016
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Who Ate My dBs?5/1/2016
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Unfiltered Analog9/1/2015
Software & Systems Requirements
Evaluation Software
JESD204 Interface Framework
Integrated JESD204 software framework for rapid system-level development and optimization
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
S-Parameters
ZIP
AD9680 S-Parameters
459.98 K
Design Tools
Companion Transport Layer RTL Code Generator Tool (Rev. 1.0)
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
JESD204x Frame Mapping Table Generator
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
Visual Analog
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
ADIsimRF
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
ZIP
AD9680 Delphi Models
1.39 K
Product Recommendations
AD9680 Companion Parts
Recommended Differential Driver Amplifiers
- For a low output noise, RF differential amplifier for driving heavy loads: ADA4961.
- For ultrahigh dynamic range, low distortion and low noise: ADL5565.
Recommended Power Products
Recommended Clock Distribution Device
Recommended Clock Generation Device
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
| Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
|---|---|---|---|---|
| AD9680BCPZ-1000 | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
| AD9680BCPZ-1250 | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
| AD9680BCPZ-500 | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
| AD9680BCPZ-820 | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
| AD9680BCPZRL7-1000 | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
| AD9680BCPZRL7-1250 | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
| AD9680BCPZRL7-500 | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
| AD9680BCPZRL7-820 | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
| Wafer Fabrication Data |
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.