Overview

Features and Benefits

  • Flexible reconfigurable radio common platform design
    • 4D2A (4 × 3 GSPS to 12 GSPS DAC and 2 × 3 GSPS to 6 GSPS ADC)
    • 4D1A (4 × 3 GSPS to 12 GSPS DAC and 1 × 3 GSPS to 6 GSPS ADC)
    • RF DAC/RF ADC output/input −3 dB bandwidth of 5.2 GHz and 7.5 GHz
    • Transmit/receive channel bandwidth up to 1.6 GHz/3 GHz (4T2R)
    • Transmit/receive channel bandwidth up to 2.4 GHz/3 GHz (2T2R)
    • On-chip PLL (6 GHz to 12 GHz) with multichip synchronization; output clock provided
      • External RFCLK input option
  • AC performance target
    • ADC test conditions (6 GSPS, −1 dBFS, fIN < 1.4 GHz)
      • NSD = −154 dBFS/Hz; HD2 < −70 dBc; HD3 < −70 dBc; SFDR (excluding HD2, HD3) <−78 dBc; IL < −75 dBc
    • DAC Test conditions (6 GSPS, −7 dBFS, 1.8 GHz)
      • NSD = −158 dBFS/Hz; SFDR < −74 dBc
  • Versatile Digital Features
    • Supports real or complex digital data (8-, 12, or 16-bit)
    • Configurable DDC/DUC
      • 8 fine complex DUCs and 4 coarse complex DUCs
      • 8 fine complex DDCs and 4 coarse complex DDCs
      • 2 independent NCOs per DUC/DDC
      • Option to bypass fine and coarse DUC/DDC
    • Programmable 192-tap FIR filter
  • RxAGC Support
    • Fast Detect with low latency for fast AGC control
    • Signal Monitor for slow AGC control
    • Dedicated AGC support pins
  • Transmit DPD support
    • Fine DUC channel gain control and delay adjust
    • Coarse DDC delay adjust for ADC observation path
  • Auxiliary Features
    • Fast frequency hopping
    • Low latency Digital Loopback Mode (ADC to DAC)
    • ADC clock driver with selectable divide ratios
    • PA downstream protection circuitry
    • On-chip Temp Sensor
    • Flexible GPIO pins
    • ADC clock driver with selectable divide ratios
    • Power amplifier downstream protection circuitry
    • On-chip temperature sensor
    • Programmable GPIO pins
    • TDD power savings option
  • SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps
    • 8 receive lanes for RF DAC
    • 8 transmit lanes for RF AD
    • 204B compatible with the maximum 15.5 Gbps lane rate
    • 204C compatible with the max 24.75Gbps lane rate
    • 204C compatible with the maximum 24.75 Gbps lane rate
    • Sample/bit repeat mode for receive lane rate matching
  • Target typical ~ 6 W to 7 W
  • 15 mm × 15 mm BGA with 0.8 mm pitch

Product Details

The transmit signal front end (MxFE®) is a highly integrated device with 16-bit, 12 GSPS maximum sample rate radio frequency (RF) digital-to-analog converter (DAC) core and 12-bit, 6 GSPS rate RF analog-to-digital (ADC) core. The AD9082 is able to support four transmitter channels and two receiver channels with 4D2A configuration. This product is well suited for two- and four-antenna transmitter applications requiring wideband ADCs for the digital predistortion observation path. It features a 16-lane, 24.75 Gbps JESD204C or 15.5 Gbps JESD204B data transceiver port, an on-chip clock multiplier, and digital signal processing capability targeted at multiband direct-to-RF radio applications. It supports up to 6 GSPS complex transmit and receive data rates in single channel mode. The maximum radio band spacing supported in multichannel modes is 1.2 GHz.The AD9082 features a bypassable interpolator and decimator for achieving ultrawideband capability along with low latency loop back and frequency hopping modes targeted at phase array radar system and electronic warfare jammer applications.

Applications

  • Wireless communications infrastructure
  • W-CDMA, LTE, LTE-A, Massive-MIMO
  • Microwave point-to-point and E-Band and 5G mm Wave
  • Broadband communications systems
  • DOCSIS 3.0 CMTS
  • Phased array radar and electronic warfare
  • Electronic test and measurement systems

Product Lifecycle icon-recommended Pre-Release

This product is new and engineering validation may still be underway. Quantities may be limited and design specifications may change while we ready the product for release to production.

Design Resources

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.


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