AD9152
RECOMMENDED FOR NEW DESIGNSDual, 16-Bit, 2.25 GSPS, TxDAC+ Digital-to-Analog Converter
- Part Models
- 2
- 1ku List Price
- Starting From $57.78
Part Details
- Supports input data rates up to 1.125 GSPS
- Proprietary low spurious and distortion design
- Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc
at 180 MHz IF - SFDR = 72 dBc at 150 MHz IF, −6 dBFS
- Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc
- Flexible 4-lane JESD204B interface
- Multiple chip synchronization
- Fixed latency
- Data generator latency compensation
- Selectable 1×, 2×, 4×, and 8× interpolation filter
- Low power architecture
- Input signal power detection
- Emergency stop for downstream analog circuitry protection
- Transmit enable function allows extra power saving
- High performance, low noise, phase-locked loop (PLL) clock multiplier
- Digital inverse sinc filter and programmable finite impulse response (FIR) filter
- Low power: 1223 mW at 1.5 GSPS, 1406 mW at 2.0 GSPS, full operating conditions
- 56-lead LFCSP with exposed pad
The AD9152 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.25 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM) from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9152 is available in a 56-lead LFCSP. The AD9152 is a member of the TxDAC+® family.
PRODUCT HIGHLIGHTS
- Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications.
- Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies.
- JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design.
- Fewer pins for data interface width with the serializer/deserializer (SERDES) JESD204B four-lane interface.
- Programmable transmit enable function allows easy design balance between power consumption and wake-up time.
- Small package size with an 8 mm × 8 mm footprint.
APPLICATIONS
-
Wireless communications
- Multicarrier LTE and GSM base stations
- Wideband repeaters
- Software defined radios
- Wideband communications
- Point to point microwave radios
- LMDS/MMDS
- Transmit diversity, multiple input/multiple output (MIMO)
- Instrumentation
- Automated test equipment
Documentation
Data Sheet 1
Informational 1
Device Drivers 2
FPGA Interoperability Reports 4
Webcast 2
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9152BCPZ | 56-Lead LFCSP (8mm x 8mm w/ EP) | ||
| AD9152BCPZRL | 56-Lead LFCSP (8mm x 8mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Jun 14, 2021 - 20_0353 Assembly Site Transfer of Select LFCSP Products to ASE Korea |
||
| AD9152BCPZ | PRODUCTION | |
| AD9152BCPZRL | PRODUCTION | |
|
Sep 1, 2016 - 16_0170 AD9152 Die Revision and Data Sheet Update |
||
| AD9152BCPZ | PRODUCTION | |
| AD9152BCPZRL | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Evaluation Software 2
JESD204x Frame Mapping Table Generator
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
JESD204 Interface Framework
Integrated JESD204 software framework for rapid system-level development and optimization
Can't find the software or driver you need?
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 3 | ||
| LTC6953 | LAST TIME BUY | Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support |
| HMC7043 | RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C |
| HMC6832 | LAST TIME BUY | Low Noise, 2:8 Differential, Fanout Buffer |
| Clock Generation Devices 2 | ||
| LTC6952 | LAST TIME BUY | Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
| HMC7044 | RECOMMENDED FOR NEW DESIGNS | High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
Tools & Simulations
DAC Companion Transport Layer RTL Code Generator
These command line executable tool generates a Verilog module which implements the JESD204 transmitter transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
Open ToolIBIS Model 1
AD9144/AD9152/AD9154/AD9135/AD9136 AMI Model Download
Open ToolLTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.
Evaluation Kits
FPGA Based Data Capture Kit
Resources
AD9152 Evaluation Board
Resources
ADS8-V1 Evaluation Board
Resources
High speed data acquisition FMC board