Overview

Features and Benefits

  • SNR = 79.9 dBFS at 16 MHz (VREF = 1.4 V) 
  • SNR = 78.1 dBFS at 64 MHz (VREF = 1.4 V) 
  • SFDR = 86 dBc to Nyquist (VREF = 1.4 V) 
  • JESD204B Subclass 1 coded serial digital outputs 
  • Flexible analog input range: 2.0 V p-p to 2.8 V p-p 
  • 1.8 V supply operation 
  • Low power: 197 mW per channel at 125 MSPS (two lanes) 
  • DNL = ±0.6 LSB (VREF = 1.4 V) 
  • INL = ±4.5 LSB (VREF = 1.4 V) 
  • 650 MHz analog input bandwidth, full power 
  • Serial port control 
    • Full chip and individual channel power-down modes 
    • Built-in and custom digital test pattern generation 
    • Multichip sync and clock divider 
    • Standby mode

Product Details

The AD9656 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample and hold circuit designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. An external reference or driver components are not required for many applications.

Individual channel power-down is supported and typically consumes less than 14 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable output clock, data alignment, and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudo-random patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

The AD9656 is available in an RoHS compliant, nonmagnetic, 56-lead LFCSP. It is specified over the −40°C to +85°C industrial temperature range.


Product Highlights

  1. It has a small footprint. Four ADCs are contained in a small, 8 mm × 8 mm package. 
  2. An on-chip phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock. 
  3. The configurable JESD204B output block supports up to 8.0 Gbps per lane. 
  4. JESD204B output block supports one, two, and four lane configurations. 
  5. Low power of 198 mW per channel at 125 MSPS, two lanes.
  6. The SPI control offers a wide range of flexible features to meet specific system requirements.


Applications

  • Medical imaging
  • High speed imaging
  • Quadrature radio receivers
  • Diversity radio receivers
  • Portable test equipment

Product Lifecycle icon-recommended Recommended for New Designs

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

Evaluation Kits (1)

Tools & Simulations

Design Tools

Companion Transport Layer RTL Code Generator Tool (Rev. 1.0)

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

JESD204x Frame Mapping Table Generator

The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.

Visual Analog

For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.

Product Recommendations

AD9656 Companion Parts

Recommended Driver Amplifiers

  • For a high speed, low power, FET input: AD822.
  • For RF/IF applications requiring low noise and low distortion: ADL5565.
  • For baseband applications requiring ultra low noise, low distortion, low power: ADA4930-1.

Recommended Clock Drivers

  • For high performance clock generation in a JESD204B system: AD9528.
  • For low jitter clock buffering in a JESD204B system
    : HMC7043.

Recommended Power Devices

  • For a high efficiency, low quiescent current, DC- DC converter: ADP2108.
  • For a low dropout, CMOS linear regulator: ADP1706.

Design Resources

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

PCN-PDN Information

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Evaluation Boards Pricing displayed is based on 1-piece.
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.