Features and Benefits
- SNR = 79.9 dBFS at 16 MHz (VREF = 1.4 V)
- SNR = 78.1 dBFS at 64 MHz (VREF = 1.4 V)
- SFDR = 86 dBc to Nyquist (VREF = 1.4 V)
- JESD204B Subclass 1 coded serial digital outputs
- Flexible analog input range: 2.0 V p-p to 2.8 V p-p
- 1.8 V supply operation
- Low power: 197 mW per channel at 125 MSPS (two lanes)
- DNL = ±0.6 LSB (VREF = 1.4 V)
- INL = ±4.5 LSB (VREF = 1.4 V)
- 650 MHz analog input bandwidth, full power
- Serial port control
- Full chip and individual channel power-down modes
- Built-in and custom digital test pattern generation
- Multichip sync and clock divider
- Standby mode
The AD9656 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample and hold circuit designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. An external reference or driver components are not required for many applications.
Individual channel power-down is supported and typically consumes less than 14 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable output clock, data alignment, and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudo-random patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
The AD9656 is available in an RoHS compliant, nonmagnetic, 56-lead LFCSP. It is specified over the −40°C to +85°C industrial temperature range.
- It has a small footprint. Four ADCs are contained in a small, 8 mm × 8 mm package.
- An on-chip phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock.
- The configurable JESD204B output block supports up to 8.0 Gbps per lane.
- JESD204B output block supports one, two, and four lane configurations.
- Low power of 198 mW per channel at 125 MSPS, two lanes.
- The SPI control offers a wide range of flexible features to meet specific system requirements.
- Medical imaging
- High speed imaging
- Quadrature radio receivers
- Diversity radio receivers
- Portable test equipment
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
The AD9656EBZ is an evaluation board for the AD9656, quad 16-bit ADC. This reference design provides all of the support circuitry required to operate the devices in their various modes and configurations. It is designed to interface directly with the HSC-ADC-EVALEZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device's hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI Controller software package is also compatible with this hardware, and allows the user to access the SPI programmable features of the AD9656.
The AD9656 data sheet provides additional information related to device configuration and performance, and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email email@example.com
Features & Benefits
- 6V 2A switching supply (such as CUI EPS060250UH-PHP-SZ) (optional)
- 12V, 3 A switching power supply
- Analog signal source and anti aliasing filter
- Analog Clock source (if not using the on-board crystal)
- PC running Windows
- USB 2.0 port recommended (USB 1.1 compatible)
- AD9656 Evaluation Board (AD9656EBZ)
- HSC-ADC-EVALEZ Data Capture Board
Tools & Simulations
AD9656 Companion Parts
Recommended Driver Amplifiers
- For a high speed, low power, FET input: AD822.
- For RF/IF applications requiring low noise and low distortion: ADL5565.
- For baseband applications requiring ultra low noise, low distortion, low power: ADA4930-1.
Recommended Clock Drivers
FPGA Interoperability Reports (1)
Technical Articles (1)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.