AD9656
Quad, 16-Bit, 125 MSPS JESD204B 1.8 V Analog-to-Digital Converter
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- SNR = 79.9 dBFS at 16 MHz (VREF = 1.4 V)
- SNR = 78.1 dBFS at 64 MHz (VREF = 1.4 V)
- SFDR = 86 dBc to Nyquist (VREF = 1.4 V)
- JESD204B Subclass 1 coded serial digital outputs
- Flexible analog input range: 2.0 V p-p to 2.8 V p-p
- 1.8 V supply operation
- Low power: 197 mW per channel at 125 MSPS (two lanes)
- DNL = ±0.6 LSB (VREF = 1.4 V)
- INL = ±4.5 LSB (VREF = 1.4 V)
- 650 MHz analog input bandwidth, full power
- Serial port control
- Full chip and individual channel power-down modes
- Built-in and custom digital test pattern generation
- Multichip sync and clock divider
- Standby mode
The AD9656 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample and hold circuit designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. An external reference or driver components are not required for many applications.
Individual channel power-down is supported and typically consumes less than 14 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable output clock, data alignment, and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudo-random patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
The AD9656 is available in an RoHS compliant, nonmagnetic, 56-lead LFCSP. It is specified over the −40°C to +85°C industrial temperature range.
Product Highlights
- It has a small footprint. Four ADCs are contained in a small, 8 mm × 8 mm package.
- An on-chip phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock.
- The configurable JESD204B output block supports up to 8.0 Gbps per lane.
- JESD204B output block supports one, two, and four lane configurations.
- Low power of 198 mW per channel at 125 MSPS, two lanes.
- The SPI control offers a wide range of flexible features to meet specific system requirements.
Applications
- Medical imaging
- High speed imaging
- Quadrature radio receivers
- Diversity radio receivers
- Portable test equipment
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AD9656
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ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
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AD9656BCPZ-125 | 56-Lead LFCSP (8mm x 8mm w/ EP) |
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AD9656BCPZRL7-125 | 56-Lead LFCSP (8mm x 8mm w/ EP) |
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- AD9656BCPZ-125
- Pin/Package Drawing
- 56-Lead LFCSP (8mm x 8mm w/ EP)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
- AD9656BCPZRL7-125
- Pin/Package Drawing
- 56-Lead LFCSP (8mm x 8mm w/ EP)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
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Part Models
Product Lifecycle
PCN
Jan 18, 2017
- 16_0079
AD9656 Datasheet Specification Updates
AD9656BCPZ-125
PRODUCTION
AD9656BCPZRL7-125
PRODUCTION
Filter by Model
Part Models
Product Lifecycle
PCN
Jan 18, 2017
- 16_0079
AD9656 Datasheet Specification Updates
Software & Part Ecosystem
Device Drivers
Looking for Evaluation Software? You can find it here
Parts | Product Life Cycle | Description | ||
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Clock Distribution Devices1 |
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RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C |
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Clock Generation Devices1 |
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RECOMMENDED FOR NEW DESIGNS |
JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs |
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Fully Differential Amplifiers1 |
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RECOMMENDED FOR NEW DESIGNS |
6 GHz Ultrahigh Dynamic Range Differential Amplifier |
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Internal Power Switch Buck Regulators1 |
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PRODUCTION |
Compact, 600 mA, 3 MHz, Step-Down DC-to-DC Converter |
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Low Input Bias Current Op Amps (≤100 pA)1 |
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PRODUCTION |
Single-Supply, Rail-to-Rail Low Power FET-Input Dual Op Amp |
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Positive Linear Regulators (LDO)1 |
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PRODUCTION |
1 A, Low Dropout, CMOS Linear Regulator |
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Single-Ended to Differential Amplifiers1 |
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RECOMMENDED FOR NEW DESIGNS |
Ultralow Noise Drivers for Low Voltage ADCs |
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
Can't find the software or driver you need?
Request a Driver/SoftwareEvaluation Kits 1
EVAL-AD9656
AD9656 Evaluation Board
Product Detail
The AD9656 data sheet provides additional information related to device configuration and performance, and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeed.converters@analog.com
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