AD9172
Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
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Features
- Supports multiband wireless applications
- 3 bypassable, complex data input channels per RF DAC
- 1.54 GSPS maximum complex input data rate per input channel
- 1 independent NCO per input channel
- Proprietary, low spurious and distortion design
- 2-tone intermodulation distortion (IMD) = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output
- Spurious free dynamic range (SFDR) <−80 dBc at 1.8 GHz, −7 dBFS RF output
- Flexible 8-lane, 15.4 Gbps JESD204B interface
- Supports single-band and multiband use cases
- Supports 12-bit high density mode for increased data throughput
- Multiple chip synchronization
- Supports JESD204B Subclass 1
- Selectable interpolation filter for a complete set of input data rates
- 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation
- 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation
- Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz
- Transmit enable function allows extra power saving and downstream circuitry protection
- High performance, low noise PLL clock multiplier
- Supports 12.6 GSPS DAC update rate
- Observation ADC clock driver with selectable divide ratios
- Low power
- 2.55 W at 12 GSPS, dual channel mode
- 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch
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The AD9172 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 12.6 GSPS. The device features an 8-lane, 15 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency (RF) wireless applications.
The AD9172 features three complex data input channels per RF DAC that are bypassable. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, multiband frequency planning. The device supports up to a 1.5 GSPS complex data rate per input channel and is capable of aggregating multiple complex input data streams up to a maximum complex data rate of 1.5 GSPS. Additionally, the AD9172 supports ultrawide bandwidth modes bypassing the channelizers to provide maximum data rates of up to 3.08 GSPS (with 16-bit resolution) and 4.1 GSPS (with 12-bit resolution).
The AD9172 is available in a 144-ball BGA_ED package.
PRODUCT HIGHLIGHTS
- Supports single-band and multiband wireless applications with three bypassable complex data input channels per RF DAC at a maximum complex input data rate of 1.5 GSPS. One independent NCO per input channel.
- Ultrawide bandwidth channel bypass modes supporting up to 3 GSPS data rates with 16-bit resolution and 4 GSPS with 12-bit resolution.
- Low power dual converter decreases the amount of power consumption needed in high bandwidth and multichannel applications.
APPLICATIONS
- Wireless communications infrastructure
- Multiband base station radios
- Microwave/E-band backhaul systems
- Instrumentation, automatic test equipment (ATE)
- Radars and jammers
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AD9172
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ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
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| AD9172BBPZ |
144 ball (10x10x1.71 w/6.6 mm EP)
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| AD9172BBPZRL |
144 ball (10x10x1.71 w/6.6 mm EP)
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144 ball (10x10x1.71 w/6.6 mm EP)
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HTML
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SamacSys
- AD9172BBPZRL
- Pin/Package Drawing
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144 ball (10x10x1.71 w/6.6 mm EP)
- Documentation
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HTML
Material Declaration
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HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
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SamacSys
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PCN
Oct 22, 2021
- 19_0097
CANCELLED: Data Sheet and Die Revision for AD9171/AD9172/AD9173
AD9172BBPZ
PRODUCTION
AD9172BBPZRL
PRODUCTION
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Oct 22, 2021
- 19_0097
CANCELLED: Data Sheet and Die Revision for AD9171/AD9172/AD9173
AD9172BBPZ
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AD9172BBPZRL
PRODUCTION
Software & Part Ecosystem
Device Drivers
Code Examples
AD917x API - Download Source Code Package
Looking for Evaluation Software? You can find it here
| Parts | Product Life Cycle | Description | ||
|---|---|---|---|---|
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Clock Generation Devices2 |
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LAST TIME BUY |
Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
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Phase Locked Loop with Integrated VCO1 |
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RECOMMENDED FOR NEW DESIGNS |
Microwave Wideband Synthesizer with Integrated VCO |
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The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
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Request a Driver/SoftwareEvaluation Kits 2
ADS8-V1EBZ
ADS8-V1 Evaluation Board
Product Detail
When connected to a specified Analog Devices high speed adc evaluation board, the ADS8-V1 works as a data acquistion board. Designed to support the highest speed JESD204B A/D Converters, the FPGA on the ADS8-V1 acts as the data receiver, while the ADC is the data transmitter.
Resources
EVAL-AD917x
AD917x Evaluation Board
Product Detail
To operate the evaluation board, the user must attach the board to a compatible FMC carrier board, such as those provided by FPGA vendors. Analog Devices produces an FPGA carrier called the ADS7-V2, which serves as a digital pattern generator or data source as well as the power supply for the boards. The AD917x board has an option to be powered from a lab power supply when used in a special NCO-only mode. This operation is described in more detail in the User's Guide, linked on the wiki site. The user must be able to observe the DAC output on a spectrum analyzer. A low noise clock source is provided on the evaluations boards, the HMC7044 clock synthesizer, and an option exists for the user to supply a low jitter external sine or square wave clock as a clock source instead. The evaluation board comes with software, called ACE, which allows the user to program the SPI port. Via the SPI port, the DUT (and clock circuitry) can be programmed into any of its various operating modes. It also comes with the DAC Software Suite which includes the DPGDownloader for vector generation, download, and transmission to the evaluation board when using the ADS7-V2.
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S-Parameter
