AD9250
Info : RECOMMENDED FOR NEW DESIGNS
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AD9250

14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 4
1ku List Price Starting From $93.08
Features
  • JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
  • Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and 250 MSPS
  • Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN and 250 MSPS
  • Total power consumption: 711 mW at 250 MSPS
  • 1.8 V supply voltages
  • Integer 1-to-8 input clock divider
  • Sample rates of up to 250 MSPS
  • IF sampling frequencies of up to 400 MHz
  • Internal analog-to-digital converter (ADC) voltage reference
  • Flexible analog input range
    • 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
  • ADC clock duty cycle stabilizer (DCS)
  • 95 dB channel isolation/crosstalk
  • Serial port control
  • Energy saving power-down modes
Additional Details
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The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.

The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.

By default, the ADC output data is routed directly to the two JESD204B serial output lanes. These outputs are at CML voltage levels. Four modes support any combination of M = 1 or 2 (single or dual converters) and L = 1 or 2 (one or two lanes). For dual ADC mode, data can be sent through two lanes at the maximum sampling rate of 250 MSPS. However, if data is sent through one lane, a sampling rate of up to 125 MSPS is supported. Synchronization inputs (SYNCINB± and SYSREF±) are provided.

Flexible power-down options allow significant power savings, when desired. Programmable overrange level detection is supported for each channel via the dedicated fast detect pins.

Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.

The AD9250 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

Product Highlights

  1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
  2. The configurable JESD204B output block supports up to 5 Gbps per lane.
  3. An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock.
  4. Support for an optional RF clock input to ease system board design.
  5. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz.
  6. Operation from a single 1.8 V power supply.
  7. Standard serial port interface (SPI) that supports various product features and functions such as controlling the clock DCS, power-down, test modes, voltage reference mode, over range fast detection, and serial output configuration.

Applications

  • Diversity radio systems
  • Multimode digital receivers (3G)
    • TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
  • DOCSIS 3.0 CMTS upstream receive paths
  • HFC digital reverse path receivers
  • I/Q demodulation systems
  • Smart antenna systems
  • Electronic test and measurement equipment
  • Radar receivers
  • COMSEC radio architectures
  • IED detection/jamming systems
  • General-purpose software radios
  • Broadband data applications
AD9250 wins Best Electronic Design 2012 Award!
Part Models 4
1ku List Price Starting From $93.08

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9250BCPZ-170
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AD9250BCPZ-250
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AD9250BCPZRL7-170
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AD9250BCPZRL7-250
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Software & Part Ecosystem

Software & Part Ecosystem

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Evaluation Kit

Evaluation Kits 3

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EVAL-AD9250

AD9250 Evaluation Board

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EVAL-AD9250

AD9250 Evaluation Board

AD9250 Evaluation Board

Features and Benefits

  • Full featured evaluation board for the AD9250
  • SPI interface for setup and control
  • External clocking option
  • Balun/transformer or amplifier input drive option
  • LDO regulator or switching power supply options
  • VisualAnalog® and SPI controller software interfaces

Product Detail

The AD9250-250EBZ is an evaluation board for the AD9250, dual, 14-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations. It is designed to interface directly with the HSC-ADC-EVALCZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9250.

The AD9250 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeedproductssupport@analog.com.

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AD-FMCJESDADC1-EBZ

AD-FMCJESDADC1-EBZ Rapid Development Board

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AD-FMCJESDADC1-EBZ

AD-FMCJESDADC1-EBZ Rapid Development Board

AD-FMCJESDADC1-EBZ Rapid Development Board

Product Detail

The AD-FMCJESDADC1-EBZ is an easy-to-use FMC-based rapid development board comprising four 14-bit, 250 MSPS, A/D conversion channels and featuring a JESD204B high-speed serial output interface. The board contains two AD9250 dual-channel ADC ICs with on-board clocking and power supplies to facilitate seamless connectivity with the Xilinx ML605, KC705 or VC707 development platform.

 

Note

The AD-FMCJESDADC1-EBZ Rapid Prototyping module’s primary purpose is to facilitate understanding/validating/verifying the JESD204B interface within the FPGA development platform ecosystem. This module was designed to comply with all of the FMC physical specifications in terms of mechanical size and mounting hole locations, and as such, PCB layout tradeoffs were made which impact wideband ac performance in the first Nyquist zone. If your objective is AD9250 performance evaluation, please refer to the performance-optimized evaluation boards; their information can be found here.

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HSC-ADC-EVALEZ

FPGA Based Data Capture Kit

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HSC-ADC-EVALEZ

FPGA Based Data Capture Kit

FPGA Based Data Capture Kit

Features and Benefits

  • 256kB FIFO Depth
  • Supports multiple ADC channels via single FMC-HPC interface connector
  • JESD-204B support for up to eight (8) 6.5Gbps Lanes
  • Parallel input at 644 MSPS SDR and 1.2 GSPS DDR
  • Use with VisualAnalog® software
  • Based on Virtex-6 FPGA
  • Simple USB port interface (2.0)

Product Detail

The HSC-ADC-EVALEZ FMC-Compatible high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up and supports emerging serial interface standards, like JESD204B. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.
Tools & Simulations

Tools & Simulations 7

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