Features and Benefits
- JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
- Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and 250 MSPS
- Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN and 250 MSPS
- Total power consumption: 711 mW at 250 MSPS
- 1.8 V supply voltages
- Integer 1-to-8 input clock divider
- Sample rates of up to 250 MSPS
- IF sampling frequencies of up to 400 MHz
- Internal analog-to-digital converter (ADC) voltage reference
- Flexible analog input range
- 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
- ADC clock duty cycle stabilizer (DCS)
- 95 dB channel isolation/crosstalk
- Serial port control
- Energy saving power-down modes
The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.
The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.
By default, the ADC output data is routed directly to the two JESD204B serial output lanes. These outputs are at CML voltage levels. Four modes support any combination of M = 1 or 2 (single or dual converters) and L = 1 or 2 (one or two lanes). For dual ADC mode, data can be sent through two lanes at the maximum sampling rate of 250 MSPS. However, if data is sent through one lane, a sampling rate of up to 125 MSPS is supported. Synchronization inputs (SYNCINB± and SYSREF±) are provided.
Flexible power-down options allow significant power savings, when desired. Programmable overrange level detection is supported for each channel via the dedicated fast detect pins.
Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.
The AD9250 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
- Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
- The configurable JESD204B output block supports up to 5 Gbps per lane.
- An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock.
- Support for an optional RF clock input to ease system board design.
- Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz.
- Operation from a single 1.8 V power supply.
- Standard serial port interface (SPI) that supports various product features and functions such as controlling the clock DCS, power-down, test modes, voltage reference mode, over range fast detection, and serial output configuration.
- Diversity radio systems
- Multimode digital receivers (3G)
- TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
- I/Q demodulation systems
- Smart antenna systems
- Electronic test and measurement equipment
- Radar receivers
- COMSEC radio architectures
- IED detection/jamming systems
- General-purpose software radios
- Broadband data applications
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (3)
The user guide describes the AD9250/AD6673 evaluation boards that can be used to evaluate Analog Devices, Inc., high speed AD9250-250, AD9250-170, or the AD6673-250 ADCs.
This evaluation board is obsolete and no longer recommended.
The CVT-ADC-FMC-INTPZB was developed in 2012 to serve as a temporary bridge between certain legacy ADI Tyco connector EVBs and the newer, industry-standard FMC-style connectors on certain COTS Xilinx FPGA platforms. The interposer was only verified for compatibility between specific ADI Converter EVBs and specific 3rd-party Xilinx COTS FPGA platforms listed here: https://wiki.analog.com/resources/alliances/xilinx#ad-adc-fmc_adapter_board
Please note that the CVT-ADC-FMC-INTPZ only supported the small subset of converter boards listed at the above link.
At this point the majority of the legacy Tyco eval brds previously supported by the CVT-ADC-FMC-INTPZ have either been obsolesced or redesigned using the new FMC-compatible connector. The decision was made to obsolete the interposer since it was no longer required/universally supported.
The AD-FMCJESDADC1-EBZ is an easy-to-use FMC-based rapid development board comprising four 14-bit, 250 MSPS, A/D conversion channels and featuring a JESD204B high-speed serial output interface. The board contains two AD9250 dual-channel ADC ICs with on-board clocking and power supplies to facilitate seamless connectivity with the Xilinx ML605, KC705 or VC707 development platform.
The AD-FMCJESDADC1-EBZ Rapid Prototyping module’s primary purpose is to facilitate understanding/validating/verifying the JESD204B interface within the FPGA development platform ecosystem. This module was designed to comply with all of the FMC physical specifications in terms of mechanical size and mounting hole locations, and as such, PCB layout tradeoffs were made which impact wideband ac performance in the first Nyquist zone. If your objective is AD9250 performance evaluation, please refer to the performance-optimized evaluation boards; their information can be found here.
Software & Systems Requirements
JESD204 Interface Framework
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
AD9250 Companion Parts
Recommended Clock Drivers
- For low jitter performance: AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9525.
- For low jitter performance and integrated VCO: AD9516-3, AD9516-4.
- For low jitter performance with jitter cleaning capability: AD9523, AD9523-1, AD9524.
Recommended Driver Amplifiers
Technical Articles (10)
Analog Dialogue (1)
Press Releases (4)
Rarely Asked Questions (1)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.