Overview

Features and Benefits

  • JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
  • Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and 250 MSPS
  • Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN and 250 MSPS
  • Total power consumption: 711 mW at 250 MSPS
  • 1.8 V supply voltages
  • Integer 1-to-8 input clock divider
  • Sample rates of up to 250 MSPS
  • IF sampling frequencies of up to 400 MHz
  • Internal analog-to-digital converter (ADC) voltage reference
  • Flexible analog input range
    • 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
  • ADC clock duty cycle stabilizer (DCS)
  • 95 dB channel isolation/crosstalk
  • Serial port control
  • Energy saving power-down modes

Product Details

The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.

The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.

By default, the ADC output data is routed directly to the two JESD204B serial output lanes. These outputs are at CML voltage levels. Four modes support any combination of M = 1 or 2 (single or dual converters) and L = 1 or 2 (one or two lanes). For dual ADC mode, data can be sent through two lanes at the maximum sampling rate of 250 MSPS. However, if data is sent through one lane, a sampling rate of up to 125 MSPS is supported. Synchronization inputs (SYNCINB± and SYSREF±) are provided.

Flexible power-down options allow significant power savings, when desired. Programmable overrange level detection is supported for each channel via the dedicated fast detect pins.

Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.

The AD9250 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

Product Highlights

  1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
  2. The configurable JESD204B output block supports up to 5 Gbps per lane.
  3. An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock.
  4. Support for an optional RF clock input to ease system board design.
  5. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz.
  6. Operation from a single 1.8 V power supply.
  7. Standard serial port interface (SPI) that supports various product features and functions such as controlling the clock DCS, power-down, test modes, voltage reference mode, over range fast detection, and serial output configuration.

Applications

  • Diversity radio systems
  • Multimode digital receivers (3G)
    • TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
  • DOCSIS 3.0 CMTS upstream receive paths
  • HFC digital reverse path receivers
  • I/Q demodulation systems
  • Smart antenna systems
  • Electronic test and measurement equipment
  • Radar receivers
  • COMSEC radio architectures
  • IED detection/jamming systems
  • General-purpose software radios
  • Broadband data applications
AD9250 wins Best Electronic Design 2012 Award!

Product Lifecycle icon-recommended Recommended for New Designs

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

Evaluation Kits (3)

Tools & Simulations

Virtual Eval - BETA

Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.

VirtualEval

Design Tools

Visual Analog

For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.

Product Recommendations

AD9250 Companion Parts

Recommended Clock Drivers

Recommended Driver Amplifiers

Design Resources

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

Discussions

AD9250 Discussions

Is there a FMCJESDADC1 program example for Linux
14 week(s) ago in Linux Software Drivers
RE: Is there a FMCJESDADC1 program example for Linux
14 week(s) ago in Linux Software Drivers
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Evaluation Boards Pricing displayed is based on 1-piece.
Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.