AD9514
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
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Overview
Features and Benefits
- 1.6 GHz differential clock input
- 3 programmable dividers
- Divide-by in range from 1 to 32
- Phase select for output-to-output coarse delay adjust
- 2 independent 1.6 GHz LVPECL clock outputs
- Additive broadband output jitter 225 fs rms
- 1 independent 800 MHz/250 MHz LVDS/CMOS clock output
- Additive broadband output jitter 300 fs rms/290 fs rms
- Time delays up to 10 ns
- Device configured with 4-level logic pins
- Space-saving, 32-lead LFCSP
Product Details
The AD9514 features a multi-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.
There are three independent clock outputs. Two of the outputs are LVPECL, and the third output can be set to either LVDS or CMOS levels. The LVPECL outputs operate to 1.6 GHz, and the third output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.
Each output has a programmable divider, which can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to another clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.
The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment.
The AD9514 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ⅓ VS. The VREF pin provides a level of ⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.
The AD9514 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.
The AD9514 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is −40°C to +85°C.
APPLICATIONS
- Low jitter, low phase noise clock distribution
- Clocking high speed ADC, DAC, DDS, DDC, DUC, MxFEs
- High performance wireless transceivers
- High performance instrumentation
- Broadband infrastructure
- ATE
Product Categories
Markets and Technologies
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
Documentation & Resources
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AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)2/14/2015PDF227 K
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AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)2/14/2015PDF291K
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AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)2/14/2015PDF0
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AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)2/14/2015PDF221 kB
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AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)2/14/2015PDF313 kB
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AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)2/14/2015PDF115 kB
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AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)2/14/2015PDF170 kB
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AN-0974: Multicarrier TD-SCMA Feasibility3/2/2010PDF634 kB
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AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)12/6/2006PDF207 kB
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AN-741: Little Known Characteristics of Phase Noise (Rev. 0)11/29/2004PDF1679 kB
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FAQs7/26/2017
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Low-power direct digital synthesizer cores enable high level of integration2/20/2008
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Improved DDS Devices Enable Advanced Comm Systems9/1/2006
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ADI Buys Korean Mobile TV Chip Maker6/7/2006
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Design A Clock-Distribution Strategy With Confidence4/27/2006
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Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems12/7/2004
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Speedy A/Ds Demand Stable Clocks3/22/2004
Tools & Simulations
Design Tools
ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
| Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
|---|---|---|---|---|
| AD9514BCPZ | Material Declaration | Reliability Data | 32-Lead LFCSP (5mm x 5mm w/ EP) | |
| AD9514BCPZ-REEL7 | Material Declaration | Reliability Data | 32-Lead LFCSP (5mm x 5mm w/ EP) | |
| Wafer Fabrication Data |
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.