AD9523
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AD9523

14-Output, Low Jitter Clock generator

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warning : NOT RECOMMENDED FOR NEW DESIGNS tooltip
warning : NOT RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 2
1ku List Price Starting From $10.67
Features
  • Output frequency: <1 MHz to 1 GHz
  • Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy)
  • Zero delay operation
    Input-to-output edge timing: <±500 ps
  • 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
  • 14 dedicated output dividers with jitterless adjustable delay
  • Adjustable delay: 8 resolution steps of ½ period of VCO output divider
  • Output-to-output skew: <±50 ps
  • Duty-cycle correction for odd divider settings
  • Automatic synchronization of all outputs on power-up
  • Nonvolatile EEPROM stores configuration settings
  • Please see data sheet for additional features
Additional Details
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The AD9523 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz.

The AD9523 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.

The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free coarse timing adjustment in increments that are equal to the period of the signal coming out of the VCO.

An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.

APPLICATIONS

  • LTE and multicarrier GSM base stations
  • Wireless and broadband infrastructure
  • Medical instrumentation
  • Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
  • Low jitter, low phase noise clock distribution
  • Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
  • Forward error correction (G.710)
  • High performance wireless transceivers
  • ATE and high performance instrumentation
Part Models 2
1ku List Price Starting From $10.67

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9523BCPZ
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AD9523BCPZ-REEL7
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Product Lifecycle

PCN

Jun 26, 2023

- 23_0025

Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor

Oct 13, 2015

- 15_0166

AD9523, AD9523-1, and AD9524 Specification Table Changes

AD9523BCPZ

PRODUCTION

AD9523BCPZ-REEL7

PRODUCTION

Feb 25, 2013

- 12_0275

AD9523 die revision

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Jun 26, 2023

- 23_0025

arrow down

Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor

Oct 13, 2015

- 15_0166

arrow down

AD9523, AD9523-1, and AD9524 Specification Table Changes

AD9523BCPZ

PRODUCTION

AD9523BCPZ-REEL7

PRODUCTION

Feb 25, 2013

- 12_0275

arrow down

AD9523 die revision

Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 1

EVAL-AD9523-1

AD9523/AD9523-1 Evaluation Board

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EVAL-AD9523-1

AD9523/AD9523-1 Evaluation Board

AD9523/AD9523-1 Evaluation Board

Features and Benefits

  • Simple power connection using USB connection and on-board LDO voltage regulators
  • LDOs are easily bypassed for power measurements
  • AC-coupled differential SMA connectors
  • SMA connectors for
    2 reference inputs
    2 PLL status outputs
    1 reference test input
    2 VCXO interface inputs/outputs
  • Microsoft Windows®–based evaluation software with simple graphical user interface
  • On-board PLL loop filter
  • Easy access to digital I/O and diagnostic signals via I/O header
  • Status LEDs for diagnostic signals
  • USB computer interface
  • Software calculator provides flexibility, allowing programming of almost any rational input/output frequency ratio

Product Detail

The AD9523-1 is designed to support the clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance. The AD9523-1 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9523-1. A 122.88 MHz VCXO is mounted on the evaluation board to provide a complete solution.


The input receivers are configured as differential but the evaluation board has baluns to provide a single-ended input for easy evaluation using common laboratory single-ended signal sources. Output 8 is connected to an ADCLK905 clock buffer to provide a way to evaluate an Analog Devices, Inc., buffer. Although the ADCLK905 is a 1-to-1 buffer, the performance is similar to the larger fanout buffer, for example, the 1-to-2 buffer, ADCLK925. Output 1 and Output 9 are configured with baluns to provide a single-ended output to drive most test equipment. Output 0 is configured for differential zero delay operation.

Tools & Simulations

Tools & Simulations 2

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