Features and Benefits
- Output frequency: <1 MHz to 1 GHz
- Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy)
- Zero delay operation
Input-to-output edge timing: <±150 ps
- 6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
- 6 dedicated output dividers with jitterless adjustable delay
- Adjustable delay: 63 resolution steps of ½ period of VCO output divider
- Output-to-output skew: <±50 ps
- Duty-cycle correction for odd divider settings
- Automatic synchronization of all outputs on power-up
- Nonvolatile EEPROM stores configuration settings
- Please see data sheet for additional features
The AD9524 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz.
The AD9524 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.
The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates six low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free coarse timing adjustment in increments that are equal to one-half the period of the signal coming out of the VCO.
An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.
- LTE and multicarrier GSM base stations
- Wireless and broadband infrastructure
- Medical instrumentation
- Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
- Low jitter, low phase noise clock distribution
- Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
- Forward error correction (G.710)
- High performance wireless transceivers
- ATE and high performance instrumentation
Markets and Technologies
Product Lifecycle Not Recommended for New Designs
This designates products ADI does not recommend broadly for new designs.
Evaluation Kits (1)
The AD9523 and AD9524 are designed to operate in the same manner.
The AD9523 is defined to support the clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive phase noise requirements necessary for acceptable data converter SNR performance.
The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a 30.72 MHz to 122.88 MHz reference clock and a VCXO of either 30.72 MHz to 122.88 MHz, the device generates low noise outputs from a range of 0.96 MHz to 983.04 MHz.
Features & Benefits
- Simple power connection using USB connection and on-board LDO voltage regulators
- LDOs are easily bypassed for power measurements
- AC-coupled differential SMA connectors
- SMA connectors for
2 reference inputs
2 PLL status outputs
1 reference test input
2 VCXO interface inputs/outputs
- Microsoft Windows®–based evaluation software with simple graphical user interface
- On-board PLL loop filter
- Easy access to digital I/O and diagnostic signals via I/O header
- Status LEDs for diagnostic signals
- USB computer interface
- Software calculator provides flexibility, allowing programming of almost any rational input/output frequency ratio
Documentation & Resources
UG-169: Evaluating the AD9523/AD9524 Clock Generator9/21/2010608 kB
RF, Microwave, and Millimeter Wave Product Selection Guide7/13/20189M
Dual-Loop Clock Generator Cleans Jitter, Provides Multiple High-Frequency Outputs1/1/2014 Analog Dialogue
Tools & Simulations
AD9524 IBIS Model
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
|Part Number||Material Declaration||Reliability Data||Pin/Package Drawing||CAD Symbols, Footprints & 3D Models|
|AD9524BCPZ||Material Declaration||Reliability Data||48-Lead LFCSP (7mm x 7mm w/ EP)|
|AD9524BCPZ-REEL7||Material Declaration||Reliability Data||48-Lead LFCSP (7mm x 7mm w/ EP)|
|Wafer Fabrication Data|
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