Features and Benefits
- JESD204B (Subclass 1) coded serial digital outputs
- Support for lane rates up to 16 Gbps per lane
- Noise density
- −152 dBFS/Hz at 2.56 GSPS at full-scale voltage = 1.7 V p-p
- −154 dBFS/Hz at 2.56 GSPS at full-scale voltage = 2.0 V p-p
- −154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p
- −155.3 dBFS/Hz at 2.0 GSPS at full-scale voltage = 2.0 V p-p
- 1.55 W total power per channel at 2.56 GSPS (default settings)
- SFDR at 2.56 GSPS encode
- 73 dBFS at 1.8 GHz AIN at −2.0 dBFS
- 59 dBFS at 5.53 GHz AIN at −2.0 dBFS
- full-scale voltage = 1.1 V p-p
- SNR at 2.56 GSPS encode
- 59.7 dBFS at 1.8 GHz AIN at −2.0 dBFS
- 53.0 dBFS at 5.53 GHz AIN at −2.0 dBFS
- full-scale voltage = 1.1 V p-p
- SFDR at 2.0 GSPS encode
- 78 dBFS at 900 MHz AIN at −2.0 dBFS
- 62 dBFS at 5.53 GHz AIN at −2.0 dBFS
- full-scale voltage = 1.1 V p-p
- SNR at 2.0 GSPS encode
- 62.7 dBFS at 900 MHz AIN at −2.0 dBFS
- 53.1 dBFS at 5.5 GHz AIN at −2.0 dBFS
- full-scale voltage = 1.1 V p-p
- 0.975 V, 1.9 V, and 2.5 V dc supply operation
- 9 GHz analog input full power bandwidth (−3 dB)
- Amplitude detect bits for efficient AGC implementation
- Programmable FIR filters for analog channel loss equalization
- 2 integrated, wideband digital processors per channel
- 48-bit NCO
- Programmable decimation rates
- Phase coherent NCO switching
- Up to 4 channels available
- Serial port control
- Supports 100 MHz SPI writes and 50 MHz SPI reads
- Integer clock with divide by 2 and divide by 4 options
- Flexible JESD204B lane configurations
- On-chip dither
The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation rates. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9689 between the DDC modes is selectable via SPI-programmable profiles.
In addition to the DDC blocks, the AD9689 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9689 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.
The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins.
The AD9689 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).
The AD9689 is available in a Pb-free, 196-ball BGA, specified over the −40°C to +85°C ambient temperature range. This product is protected by a U.S. patent.
Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.
- Wide, input −3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz.
- Four integrated, wideband decimation filters and NCO blocks supporting multiband receivers.
- Fast NCO switching enabled through the GPIO pins.
- SPI controls various product features and functions to meet specific system requirements.
- Programmable fast overrange detection and signal monitoring.
- On-chip temperature diode for system thermal management.
- 12 mm × 12 mm, 196-ball BGA.
- Pin, package, feature, and memory map compatible with the AD9208 14-bit, 3.0 GSPS, JESD204B dual ADC.
- Diversity multiband and multimode digital receivers
- 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A
- Electronic test and measurement systems
- Phased array radar and electronic warfare
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
Markets and Technologies
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (2)
AD9689 - 2600EBZ
The AD9689-2600EBZ supports the AD9689-2600, a 14-bit, 2.6GSPS dual analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed support direct RF sampling analog signals of up to 5 GHz. The 3 dB bandwidth of the ADC input is greater than 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V2EBZ data capture card, allowing users to download captured data for analysis. The device control and subsequent data analyses can now be done using the ACE software package.
When connected to a specified Analog Devices high speed adc evaluation board, the ADS8-V1 works as a data acquistion board. Designed to support the highest speed JESD204B A/D Converters, the FPGA on the ADS8-V1 acts as the data receiver, while the ADC is the data transmitter.
Documentation & Resources
28 nm Analog-to-Digital Converters Enable Next-Generation Electronic Warfare Receiver Systems6/29/2018
High Speed Amplifier Testing Involves Enough Math to Make Your Balun Spin!6/4/2018 Analog Dialogue
Radically Extending Bandwidth to Crush the X-Band Frequencies Using a Track-and-Hold Sampling Amplifier and RF ADC12/6/2017 Analog Dialogue
A Review of Wideband RF Receiver Architecture Options2/1/2017
Tools & Simulations
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.