Overview

Features and Benefits

  • JESD204B (Subclass 1) coded serial digital outputs
  • In band SFDR = 83 dBFS at 340 MHz (750 MSPS)
  • In band SNR = 66.7 dBFS at 340 MHz (750 MSPS)
  • 1.4 W total power per channel at 750 MSPS (default settings)
  • Noise density = −153 dBFS/Hz at 750 MSPS
  • 1.25 V, 2.5 V, and 3.3 V dc supply operation
  • Flexible input range
    • AD6674-750 and AD6674-1000
      • 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal)
    • AD6674-500
      • 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
  • 95 dB channel isolation/crosstalk
  • Amplitude detect bits for efficient automatic gain control (AGC) implementation
  • Noise shaping requantizer (NSR) option for main receiver function
  • Variable dynamic range (VDR) option for digital predistortion (DPD) function
  • 2 integrated wideband digital processors per channel
    • 12-bit numerically controlled oscillator (NCO), up to 4 cascaded half-band filters
  • Differential clock inputs
  • Integer clock divide by 1, 2, 4, or 8
  • Energy saving power-down modes
  • Flexible JESD204B lane configurations
  • Small signal dither

Product Details

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.

Applications

  • Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
  • DOCSIS 3.0 CMTS upstream receive paths
  • HFC digital reverse path receivers

Product Lifecycle icon-recommended Recommended for New Designs

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

Evaluation Kits (1)

Tools & Simulations

Virtual Eval - BETA

Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.

VirtualEval

IBIS Models

Design Tools

JESD204x Frame Mapping Table Generator

The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.

Companion Transport Layer RTL Code Generator Tool (Rev. 1.0)

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

Product Recommendations

AD6674 Companion Parts

Recommended Differential Driver Amplifiers

  • For a low output noise, RF differential amplifier for driving heavy loads: ADA4961.
  • For ultrahigh dynamic range, low distortion and low noise: ADL5565.

Recommended Power Products

  • For high performance, step-down switching regulators requiring high efficiency and design flexibility: ADP2164, ADP2384.
  • For a low dropout linear regulator,with adjustable output voltage settings: ADP1741.

Recommended Clock Distribution Device

Recommended Clock Generation Device

Design Resources

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

PCN-PDN Information

Sample & Buy

Sample & Buy functionality exists in desktop site
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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.


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Evaluation Boards Pricing displayed is based on 1-piece.
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.