1. Products
  2. A/D Converters (ADC)
  3. High Speed A/D Converters >10 MSPS
  4. Standard High Speed A/D Converters
  5. AD9694


Features and Benefits

  • JESD204B (Subclass 1) coded serial digital outputs
    • Lane rates up to 15 Gbps
  • 1.66 W total power at 500 MSPS
    • 415 mW per analog-to-digital converter (ADC) channel
  • SFDR = 82 dBFS at 305 MHz (1.80 V p-p input range)
  • SNR = 66.8 dBFS at 305 MHz (1.80 V p-p input range)
  • Noise density = −151.5 dBFS/Hz (1.80 V p-p input range)
  • 0.975 V, 1.8 V, and 2.5 V dc supply operation
  • No missing codes
  • Internal ADC voltage reference
  • Analog input buffer
  • On-chip dithering to improve small signal linearity
  • Flexible differential input range
    • 1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)
  • 1.4 GHz analog input full power bandwidth
  • Amplitude detect bits for efficient AGC implementation
  • 4 integrated wideband digital processors
    • 48-bit NCO, up to 4 cascaded half-band filters
  • Differential clock input
  • Integer clock divide by 1, 2, 4, or 8
  • On-chip temperature diode
  • Flexible JESD204B lane configurations

    AD9694-EP supports defense and aerospace applications (AQEC standard)

    • Download AD9694-EP Data Sheet (pdf)
    • Military temperature range (−55°C to +105°C)
    • Controlled manufacturing baseline
    • 1 assembly/test site
    • 1 fabrication site
    • Product change notification
    • Qualification data available on request 

Product Details

The AD9694 is a quad, 14-bit, 500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 1.4 GHz. The AD9694 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.

The analog inputs and clock signals are differential inputs. Each pair of ADC data outputs is internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters.

In addition to the DDC blocks, the AD9694 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.

Users can configure each pair of intermediate frequency (IF) receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins.

The AD9694 has flexible power-down options that allow significant power savings when desired. All of these features can be pro-grammed using the 1.8 V capable, 3-wire SPI.

The AD9694 is available in a Pb-free, 72-lead LFCSP and is specified over the −40°C to +105°C junction temperature range.


  1. Low power consumption per channel.
  2. JESD204B lane rate support up to 15 Gbps.
  3. Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz.
  4. Buffered inputs ease filter design and implementation.
  5. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.
  6. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.
  7. Programmable fast overrange detection.
  8. On-chip temperature diode for system thermal management.


  • Communications
  • Diversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-A
  • General-purpose software radios
  • Ultrawideband satellite receivers
  • Instrumentation
  • Radars
  • Signals intelligence (SIGINT)

Product Lifecycle icon-recommended Recommended for New Designs

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

Evaluation Kits (1)

Tools & Simulations

Virtual Eval - BETA

Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.


IBIS Models

Design Tools

Companion Transport Layer RTL Code Generator Tool (Rev. 1.0)

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

JESD204x Frame Mapping Table Generator

The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.

Product Recommendations

AD9694 Companion Parts

Recommended Clock Distribution Device

Recommended Clock Generation Device

Design Resources

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.

Part Number Material Declaration Reliability Data Pin/Package Drawing CAD Symbols, Footprints & 3D Models
AD9694BCPZ-500 Material Declaration Reliability Data 72-Lead LFCSP (10mm x 10mm w/ EP)
AD9694BCPZRL7-500 Material Declaration Reliability Data 72-Lead LFCSP (10mm x 10mm w/ EP)
AD9694TCPZ-500-EP Material Declaration Reliability Data LFCSP:LEADFRM CHIP SCALE
Wafer Fabrication Data

PCN-PDN Information

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Sample & Buy

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Evaluation Boards

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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.