Overview
Features and Benefits
- 12-bit 2.5 GSPS ADC, no missing codes
- SFDR = 79 dBc, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
- SFDR = 77 dBc, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
- SNR = 57.6 dBFS, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
- SNR = 57 dBFS, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
- Noise spectral density = −149.5 dBFS/Hz at 2.5 GSPS
- Differential analog input: 1.2 V P-P
- Differential clock input
- 3.2 GHz analog input bandwidth, full power
- High speed 6- or 8-lane JESD204B serial output Subclass 1: 6.50 Gbps at 2.6 GSPS
- Two independent decimate by 8 or decimate by 16 filters with 10-bit NCOs
- Supply voltages: 1.3 V, 2.5 V
- Flexible digital output modes
- Built-in selectable digital test patterns
- Timestamp feature
- Conversion error rate < 10−15
Product Details
The AD9625 is a 12-bit monolithic sampling analog-to-digital converter (ADC) that operates at conversion rates of up to 2.6 giga samples per second (GSPS). This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and jamming/antijamming measures.
The analog input, clock, and SYSREF± signals are differential inputs. The JESD204B-based high speed serialized output is configurable in a variety of one-, two-, four-, six-, or eight-lane configurations. The product is specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
- High performance: exceptional SFDR in high sample rate applications, direct RF sampling, and on-chip reference.
- Flexible digital data output formats based on the JESD204B specification.
- Control path SPI interface port that supports various product features and functions, such as data formatting, gain, and offset calibration values.
APPLICATIONS
- Spectrum analyzers
- Military communications
- Radar
- High performance digital storage oscilloscopes
- Active jamming/antijamming
- Electronic surveillance and countermeasures
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (6)
Documentation & Resources
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AD-FMCADC2-EBZ FMC Board User Guide1/19/2016WIKI
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JESD204 Serial Interface2/14/2015
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Validating ADI Converters Inter-operability with Xilinx FPGA and JESD204B/C IP4/10/2017PDF510 K
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Altera AN-712 (AD9625 Stratix5)10/13/2014
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Silent Switcher µModule Regulators Powering GSPS Sampling ADC3/3/2022
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60GHz/ 10Gbps Wireless platform produced by GigaFirm3/3/2022
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Using the AD9625 2.5 GSPS High Speed A/D Converter3/3/2022
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ギガファーム社製60GHz/10Gbpsワイヤレス・プラットフォームのご紹介3/3/2022
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Highest Dynamic Range 2.5 GSPS & ADC For Wideband RF Sampling6/11/2020
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Sensing, High Temperature, and High Speed Instrumentation11/28/2018
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2.6-GHz A/D Converter in High-Reliability Package Meets Specific Sample Rate and Dynamic Range Requirements of Aerospace/Defense Applications4/21/2022
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New PLLs Deliver Widest Frequency Range Coverage and Lowest VCO Phase Noise in a Single Device4/21/2022
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Analog Devices Unveils 2.5-GSPS A/D Converter, Driver Amplifier and Rapid Prototyping FMC Module4/21/2022
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Global Leader in Converter Technology Releases Industry’s Highest Performing 2-GSPS Data Converter4/21/2022
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JESD204B Subclasses—Part 2: Subclass 1 vs. Subclass 2 System Considerations10/1/2019
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JESD204B Subclasses—Part 1: An Introduction to JESD204B Subclasses and Deterministic Latency10/1/2019
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Silent Switcher µModule Regulators Quietly Power GSPS Sampling ADCs in Half the Space11/2/2018
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Analog Tips– Decimation for ADCs11/15/2017
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Use Noise Spectral Density to Evaluate ADCs in Software-Defined Systems6/1/2017
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What’s Up With Digital Downconverters—Part 17/1/2016 Analog Dialogue
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Aerospace and Defense Mobilize Insatiable Bandwidth Applications1/1/2016
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Interleaving ADCs: Unraveling the Mysteries7/1/2015 Analog Dialogue
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Taming the Wideband Conundrum with RF Sampling ADCs5/1/2015
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RF-Sampling ADC Input Protection: Not Black Magic After All4/1/2015 Analog Dialogue
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A Test Method for Synchronizing Multiple GSPS Converters2/1/2015
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GSPS Data Converters to the Rescue for Electronics Surveillance and Warfare Systems!12/1/2014
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Demystifying the Conversion Error Rate of High Speed ADCs12/1/2014
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Maximizing the Dynamic Range of Software-Defined Radio11/1/2014
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Understanding Layers in the JESD204B Specification—A High Speed ADC Perspective10/1/2014
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Gigasample ADCs Run Fast to Solve New Challenges9/1/2014
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Understanding Spurious-Free Dynamic Range in Wideband GSPS ADCs8/1/2014
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The Demand for Digital: Challenges and Solutions for High Speed Analog to Digital Converters and Radar Systems6/1/2014
Software & Systems Requirements
Evaluation Software
JESD204 Interface Framework
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.

IBIS Models
MathWorks®
Design Tools
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
PCN-PDN Information
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.