AD9213
12-Bit, 10.25 GSPS, JESD204B, RF Analog-to-Digital Converter
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Features
- High instantaneous dynamic range
- NSD
- −155 dBFS/Hz at 10 GSPS with −9 dBFS, 170 MHz input
- −153 dBFS/Hz at 10 GSPS with −1 dBFS, 170 MHz input
- SFDR: 70 dBFS at 10 GSPS with −1 dBFS, 1000 MHz input
- SFDR excluding H2 and H3 (worst other spur): 89 dBFS at 10 GSPS with −1 dBFS, 1000 MHz input
- Low power dissipation: <4.6 W typical at 10 GSPS
- Integrated input buffer (6.5 GHz input bandwidth)
- 1.4 V p-p full-scale analog input with RIN = 50 Ω
- Overvoltage protection
- 16-lane JESD204B output (up to 16 Gbps line rate)
- Multichip synchronization capable with 1 sample accuracy
- DDC NCO synchronization included
- Integrated DDC
- Selectable decimation factors
- 16 profile settings for fast frequency hopping
- Fast overrange detection for efficient AGC
- On-chip temperature sensor
- On-chip negative voltage generators
- Low CER: <1 × 10−16
- 12 mm × 12 mm, 192-ball BGA-ED package
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The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.
The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.
Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.
The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of −20°C to +115°C.
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AD9213
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System-Level LO Phase Noise Model for Phased Arrays with Distributed Phase-Locked Loops
Wideband Receiver for 5G, Instrumentation, and ADEF
28 nm Analog-to-Digital Converters Enable Next-Generation Electronic Warfare Receiver Systems
An Interview with Analog Devices Discussing RF Electronics for Phased Array Applications
A Review of Wideband RF Receiver Architecture Options
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ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9213BBPZ-10G |
192-Ball BGA_ED (12mm x 12mm x 1.56mm w/ EP)
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| AD9213BBPZ-6G |
192-Ball BGA_ED (12mm x 12mm x 1.56mm w/ EP)
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- AD9213BBPZ-10G
- Pin/Package Drawing
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192-Ball BGA_ED (12mm x 12mm x 1.56mm w/ EP)
- Documentation
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HTML
Material Declaration
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HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
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Ultra Librarian
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SamacSys
- AD9213BBPZ-6G
- Pin/Package Drawing
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192-Ball BGA_ED (12mm x 12mm x 1.56mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
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Ultra Librarian
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SamacSys
Software & Part Ecosystem
Device Drivers
Looking for Evaluation Software? You can find it here
| Parts | Product Life Cycle | Description | ||
|---|---|---|---|---|
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Clock Distribution Devices1 |
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LAST TIME BUY |
Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
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Clock Generation Devices2 |
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RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
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LAST TIME BUY |
Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
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LDO Plus1 |
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RECOMMENDED FOR NEW DESIGNS |
20V, 200mA, Ultralow Noise, Ultrahigh PSRR RF Linear Regulator |
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Multiple Output Buck Regulators2 |
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RECOMMENDED FOR NEW DESIGNS |
Dual Ultrathin 2A or Single 4A Step-Down DC/DC μModule Regulator |
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Quad DC/DC μModule (Power Module) Regulator with Configurable 4A Output Array |
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Phase Locked Loop with Integrated VCO1 |
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RECOMMENDED FOR NEW DESIGNS |
Microwave Wideband Synthesizer with Integrated VCO |
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Positive Linear Regulators (LDO)4 |
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RECOMMENDED FOR NEW DESIGNS |
2 A, Ultralow Noise, High PSRR, Fixed Output, RF Linear Regulator |
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RECOMMENDED FOR NEW DESIGNS |
4 A, Low VIN, Low Noise, CMOS Linear Regulator |
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RECOMMENDED FOR NEW DESIGNS |
300 mA, Low Quiescent Current, CMOS Linear Regulator |
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RECOMMENDED FOR NEW DESIGNS |
20V, 500mA, Ultralow Noise, Ultrahigh PSRR Linear Regulator |
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Can't find the software or driver you need?
Request a Driver/SoftwareEvaluation Kits 3
ADS8-V1EBZ
ADS8-V1 Evaluation Board
Product Detail
When connected to a specified Analog Devices high speed adc evaluation board, the ADS8-V1 works as a data acquistion board. Designed to support the highest speed JESD204B A/D Converters, the FPGA on the ADS8-V1 acts as the data receiver, while the ADC is the data transmitter.
Resources
EVAL-AD9213
AD9213 Evaluation Board
Features and Benefits
- Full featured evaluation board for the AD9213 device family.
- Wide band Balun driven input.
- No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC+ connector on ADS8-V1EBZ FPGA data capture card.
- Single software interface for device control and analysis through ACE.
Product Detail
The AD9213-10GEBZ and AD9213-6GEBZ supports the 10Gsps and 6Gsps models of the AD9213. The AD9213 is a single 12-bit, 10.25 GSPS RF analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. It has been optimized to support high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low code error rates (CER). The AD9213 features a 16-lane JESD204B interface to support its maximum bandwidth capability.
This Preliminary Evaluation design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS8-V1EBZ FPGA-based data capture card, allowing users to download captured data for analysis. The device control and subsequent data analysis can be performed using the ACE software package.
EVAL-AD9213-DUAL-EBZ
Wideband Direct RF Sampling 20GSPS Digitizer Platform
Product Detail
This dual AD9213 evaluation board is a wideband direct RF sampling 20GSPS digitizer platform which includes the two 12bit 10 GSPS RF ADCs. The RFADCs are time interleaved by 180 degrees, thus supporting a 20 GSPS sampling system. Synchronization performance is obtained to within 1 sample accuracy using the built-in multichip synchronization capabilities. The clock input interleaving is achieved by using the ADF4377, which is a low jitter microwave wideband synthesizer with an integrated VCO. This dual AD9213 reference design platform provides a path to scale up the bandwidth of interest or be used to enable end user algorithm development.
Resources
IBIS Model
