LT3045

RECOMMENDED FOR NEW DESIGNS

20V, 500mA, Ultralow Noise, Ultrahigh PSRR Linear Regulator

Data Sheet (Rev. D) Product Selection Table
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Part Details

  • Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz)
  • Ultralow Spot Noise: 2nV/√Hz at 10kHz
  • Ultrahigh PSRR: 76dB at 1MHz
  • Output Current: 500mA
  • Wide Input Voltage Range: 1.8V to 20V
  • Single Capacitor Improves Noise and PSRR
  • 100µA SET Pin Current: ±1% Initial Accuracy
  • Single Resistor Programs Output Voltage
  • High Bandwidth: 1MHz
  • Programmable Current Limit
  • Low Dropout Voltage: 260mV
  • Output Voltage Range: 0V to 15V
  • Programmable Power Good
  • Fast Start-Up Capability
  • Precision Enable/UVLO
  • Parallelable for Lower Noise and Higher Current
  • See data sheet for additional features

LT3045-EP Supports Defense and Aerospace Applications (AQEC Standard)

  • Download LT3045-EP Data Sheet (pdf)
  • Military Temperature Range (–55°C to 150°C)
  • Controlled Manufacturing Baseline
  • One Assembly/Test Site
  • One Fabrication Site
  • Product Change Notification
  • Qualification Data Available on Request
  • V62/21614 Data Sheet
LT3045
20V, 500mA, Ultralow Noise, Ultrahigh PSRR Linear Regulator
LT3045 Application Circuit LT3045 Pin Configuration LT3045 Pin Configuration LT3045 Performance Graph LT3045-EP Pin Configuration
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Documentation

Data Sheet 4

Reliability Data 1

User Guide 2

Application Note 1

Design Note 3

Technical Articles 5

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Software Resources

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Hardware Ecosystem

Parts Product Life Cycle Description
Digital Power System Managers 1
LTC2975
RECOMMENDED FOR NEW DESIGNS 4-Channel PMBus Power System Manager Featuring Accurate Input Current and Energy Measurement
Positive Linear Regulators (LDO) 1
LT1763
RECOMMENDED FOR NEW DESIGNS 500mA, Low Noise, LDO Micropower Regulators
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Tools & Simulations

LTspice 1

Models for the following parts are available in LTspice:

  • LT3045
  • LT3045-1
LTspice

LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.

Evaluation Kits

eval board
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SCP-LT3045-1-EVALZ

LT3045-1 Signal Chain Evaluation Board | 500mA Ultra Low Noise Positive LDO

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Product Details

Demonstration circuit SCP-LT3045-1-EVALZ is a 20V, 500mA Low Dropout (LDO) regulator designed best in class low noise operation in noise sensitive circuits. It is easily configured for a wide output range and can provide extremely quiet operation with its high PSRR.

Like all boards in the Signal Chain Power series, this board is designed to be easily plugged into other SCP boards to form a complete signal chain power system, enabling fast evaluation of low power signal chains. To evaluate this board, some universal SCP hardware is required, namely:

  • SCP-INPUT-EVALZ
  • SCP-OUTPUT-EVALZ
  • SCP-1X5BKOUT-EVALZ
  • SCP-THRUBRD-EVALZ
  • SCP-FILTER-EVALZ
  • SCP-1X2BKOUT-EVALZ
  • SCP-5X1-EVALZ

 

To properly evaluate SCP series demo boards, you will need the SCP Configurator companion software. SCP Configurator can help you choose the right board and topology for your design.

Note that the Demo Manual does not cover details important to the operation and configuration regarding the LT3045-1. Please refer to the LT3045-1 data sheet for a complete description of the part.

eval board
schematic 4
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DC2491A

LT3045 Demo Board | 20V, 500mA, Ultralow Noise Ultrahigh PSRR RF LDO Regulator

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Product Details

Demo circuit DC2491A features the LT3045EDD, a 500mA, ultralow noise and ultrahigh power supply rejection ratio (PSRR) low dropout (LDO) regulator with programmable current limit. DC2491A operates over an input voltage range of 3.8V to 20V. The LT3045 delivers a maximum output current of 500mA, but at this current level, thermal performance limits the maximum input voltage to 8.3V without a larger copper area or forced-air cooling.


In addition to featuring ultralow noise and ultrahigh PSRR, the regulator offers programmable power good functionality as well as programmable current limit. Current monitoring is also achieved by sensing the ILIM pin voltage. 

eval board
schematic 9
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AD-JUPITER-EBZ

Software-Defined Radio

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Features and Benefits

  • RF/SDR
    • ADRV9002 transceiver
    • 2 x receiver, 2 x transmitter
    • LO frequency range 30 MHz to 6 GHz
    • 12 kHz to 40 MHz frequency bandwidth
    • Sampling rate 12 kSPS to 61.44 MSPS
  • External Device Clock Input
  • External MCS Input
  • RF Front-end
  • Processing System
    • Zynq UltraScale+ MPSoC XCZU3EG
      • ARM Cortex-A53 1.5 GHz
      • ARM Cortex-R5 500 MHz
      • Mali-400 MP2 graphic processor
      • Programmable logic 154 k
    • DDR4 – 2 GB (x32)
    • Boot source
      • SD card 3.0
      • Flash memory 128 MB
    • User Interfaces
      • USB 3.1 Gen 1 – Type C
        • Upstream Facing Port (UFP)
        • Downstream Facing Port (DFP)
        • USB 2.0 compatible
    • Ethernet 1000BASE-T RGMII
    • Display Port v1.2 (2 lanes, 5.4 Gbps)
    • SATA 3
    • USB (micro) debug interface
    • 16 GPIOs (3V3 LVCMOS)
  • Power Sources
    • USB Type-C (power only)
      • Power Sink 5V, 9V/3A
    • USB Type-C (data)
      • Power Sink 5V/3A
      • Power Source 5V/0.9 A
    • 802.3at POE compliant, 25.5 W Type2 (POE+)

Product Details

The AD-JUPITER-EBZ is a versatile software-defined platform based on Analog Devices ADRV9002 and Xilinx Zynq UltraScale+ MPSoC. The ADRV9002 is a new generation RF transceiver that has dual-channel transmitters, dual-channel receivers covering a frequency range of 30 MHz to 6 GHz. This device has a high-quality RF linearity performance and a set of advanced features like fast profiles switching, flexible power vs. performance configuration, fast frequency hopping, multi-chip synchronization, and digital pre-distortion (DPD) for narrow and wide band waveform.

The evaluation platform includes XCZU3EG processing device that has a wide range of interfaces, making the system capable of local processing or streaming to a remote host. It comes integrated in a self-contained ruggedized aluminum case, which gives flexibility in evaluating and prototyping across different environments.

APPLICATIONS

  • Aerospace and Defense
  • Communications
  • Advanced Education
SCP-LT3045-1-EVALZ
LT3045-1 Signal Chain Evaluation Board | 500mA Ultra Low Noise Positive LDO
LT3045-1 Signal Chain Evaluation Board LT3045-1 Signal Chain Evaluation Board - Top View LT3045-1 Signal Chain Evaluation Board - Bottom View
DC2491A
LT3045 Demo Board | 20V, 500mA, Ultralow Noise Ultrahigh PSRR RF LDO Regulator
DC2491A Demo Board DC2491A Demo Board DC2491A Demo Board DC2491A Demo Board DC2491A Schematic Image
AD-JUPITER-EBZ
Software-Defined Radio
AD-JUPITER-EBZ Board Photo Angle View AD-JUPITER-EBZ Board Photo Top View AD-JUPITER-EBZ Board Photo Back View AD-JUPITER-EBZ Block Diagram

Reference Designs

Figure 1. CN0568 Block Diagram
Figure 1. CN0568 Block Diagram
CN0568 Evaluation Board - Angle View
CN0568 Evaluation Board - Top View
CN0568 Evaluation Board - Bottom View
CN0568 Circuits from the lab

Fast switching, High Performance PLL and Quadband VCO Frequency Synthesizer

View Detailed Reference Design

Features and Benefits

  • 8GHz - 26GHz Frequency Operation
  • Quadband VCO provides Low Phase Noise over Wideband
  • Onboard Reference Clock for ease of Use
  • Arduino Form Factor Compatible

Part Used

Design & Integration Tools

Videos

  • lazy blur
    VIDEO · 2022-09-02 02:36
    Ultra-Fast Switching, High Performance PLL Frequency Synthesizer
Monolithic Power Tree Solution for the ZU7 FPGA
Monolithic Power Tree Solution for the ZU7 FPGA
uModule Power Tree for the ZU7 FPGA 
ZCU104 Circuits from the lab

Zynq UltraScale+ MPSoC ZCU104 Paper Reference Design

View Detailed Reference Design

Features and Benefits

  • The ZCU104 Evaluation Kit enables designers to jumpstart designs for embedded vision applications such as surveillance, Advanced Driver Assisted Systems (ADAS), machine vision, Augmented Reality (AR), drones and medical imaging.

  • The ADI Power delivery solutions support multiple reference designs using DC/DC module and monolithic solutions. ADI offers several options for powering the Zu7 FPGA.

  • Our module-based solutions combine a small footprint, while maximizing efficiency and tight regulation. Our monolithic based solutions support a lower cost optimized power delivery solution for mass production.

  • ADI provides supporting documentation to enable you to validate the power solution for your application seamlessly.

  • For a complete list power designs and use cases, please contact your local FAE.

  • Please refer to the circuit descriptions below that best support your design.
Figure 1. CN0585 Simplified Block Diagram
Figure 1. CN0585 Simplified Block Diagram
EVAL-CN0585-FMCZ Angle View
EVAL-CN0585-FMCZ Bottom View
EVAL-CN0585-FMCZ Top View
CN0585 Circuits from the lab

Quad Channel, Low Latency, Data Acquisition and Signal Generation Module

View Detailed Reference Design

Features and Benefits

  • 4 Analog Input Channels with Configurable Voltage Ranges
  • 4 Analog Output Channels with Configurable Voltage Ranges
  • 200 ns Latency between ADC Measurement and DAC Settling
  • Analog Front End Interface Connector
  • Modeling and Simulation Compatible with MATLAB and Python
  • FMC Connector Interface to FPGA

Part Used

Resources

Design & Integration Tools

Videos

  • lazy blur
    VIDEO · 2022-10-31 03:03
    Low Latency Test and Measurement Kit – Hardware in the Loop
  • lazy blur
    VIDEO · 2023-04-03 03:08
    Personalized Low Latency Hardware in the Loop (HiL) Solution
CN0568
Fast switching, High Performance PLL and Quadband VCO Frequency Synthesizer
Figure 1. CN0568 Block Diagram
CN0568 Evaluation Board - Angle View
CN0568 Evaluation Board - Top View
CN0568 Evaluation Board - Bottom View
ZCU104
Zynq UltraScale+ MPSoC ZCU104 Paper Reference Design
Monolithic Power Tree Solution for the ZU7 FPGA
uModule Power Tree for the ZU7 FPGA 
CN0585
Quad Channel, Low Latency, Data Acquisition and Signal Generation Module
Figure 1. CN0585 Simplified Block Diagram
EVAL-CN0585-FMCZ Angle View
EVAL-CN0585-FMCZ Bottom View
EVAL-CN0585-FMCZ Top View

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