LT3094
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LT3094

−20V, 500mA, Ultralow Noise, Ultrahigh PSRR Negative Linear Regulator

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LTspice LT3094 - LDO Linear Regulators Download 1.81 KB LTspice LT3094 Demo Circuit - Ultralow Noise, Ultrahigh PSRR Negative LDO Regulator (-20V to -3.3V @ 500mA) Download 2.59 KB
Part Models 14
1ku List Price Starting From $3.37
Features
  • Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz)
  • Ultralow Spot Noise: 2.2nV/√Hz at 10kHz
  • Ultrahigh PSRR: 74dB at 1MHz
  • Output Current: 500mA
  • Wide Input Voltage Range: –1.8V to –20V
  • Single Capacitor Improves Noise and PSRR
  • 100µA SET Pin Current: ±1% Initial Accuracy
  • Single Resistor Programs Output Voltage
  • Programmable Current Limit
  • Low Dropout Voltage: 235mV
  • Output Voltage Range: 0V to –19.5V
  • Programmable Power Good and Fast Start-Up
  • Bipolar Precision Enable/UVLO Pin
  • VIOC Pin Controls Upstream Regulator to Minimize Power Dissipation and Optimize PSRR
  • Minimum Output Capacitor: 10µF Ceramic
  • 12-Lead MSOP and 3mm × 3mm DFN Packages
Additional Details
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The LT3094 is a high performance low dropout negative linear regulator featuring ADI’s ultralow noise and ultrahigh PSRR architecture for powering noise sensitive applications. The device can be easily paralleled to further reduce noise, increase output current and spread heat on a PCB.

The LT3094 supplies 500mA at a typical 235mV dropout voltage. Operating quiescent current is nominally 2.35mA and drops to 3µA in shutdown. The device’s wide output voltage range (0V to –19.5V) error amplifier operates in unity-gain and provides virtually constant output noise, PSRR, bandwidth, and load regulation independent of the programmed output voltage. Additional features are a bipolar enable pin, programmable current limit, fast startup capability and programmable power good to indicate output voltage regulation. The regulator incorporates a tracking function to control an upstream supply to maintain a constant voltage across the LT3094 to minimize power dissipation and optimize PSRR.

The LT3094 is stable with a minimum 10µF ceramic output capacitor. Built-in protection includes internal current limit with foldback and thermal limit with hysteresis. The LT3094 is available in thermally enhanced 12-Lead MSOP and 3mm × 3mm DFN Packages.

Applications

  • RF and Precision Power Supplies
  • Very Low Noise Instrumentation
  • High Speed/High Precision Data Converters
  • Medical Applications: Diagnostics and Imaging
  • Post-Regulator for Switching Supplies
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file View Data Sheet (Rev.B)
Documentation View All Documentation
LTspice LT3094 - LDO Linear Regulators Download 1.81 KB LTspice LT3094 Demo Circuit - Ultralow Noise, Ultrahigh PSRR Negative LDO Regulator (-20V to -3.3V @ 500mA) Download 2.59 KB
Part Models 14
1ku List Price Starting From $3.37
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LT3094

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UPDATED 09/25/2018
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LT3094: –20V, 500mA, Ultralow Noise, Ultrahigh PSRR Negative Linear Regulator Data Sheet (Rev.B)

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UPDATED 09/25/2018
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LT3094: –20V、500mA、超低ノイズ、超高PSRR、負電圧のリニア電圧レギュレータ データシート (Rev.0)

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SCP-LT3094-EVALZ - Demo Manual (Rev.0) redirect icon

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Design Note

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UPDATED 09/01/2019
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Negative Linear Regulator Features 0.8 µV RMS Noise and 74 dB Power Supply Rejection Ratio at 1 MHz redirect icon

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UPDATED 09/26/2019
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负线性稳压器具有0.8 µV RMS噪声和74 dB电源抑制比（1 MHz时） redirect icon

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Documentation

3rd Party Solutions 1

Mpression, Ultra-Low Noise, Ultra-High PSRR +/-12V DC/DC, Featuring LT3045 & LT3095

Solutions Bulletin & Brochure 1

Linear Low Dropout (LDO) Regulator Solutions

Rarely Asked Question Page 1

Current Noise in FET Input Amps

Webcast 1

Designing Power Solutions for RF Signal Chain Applications (EngineerZone)

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1

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2018-10-17

03:46

LT3094 - Negative LDO Features 0.8µ VRMS Noise at 1MHz

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ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
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LT3094 Data Sheet Specification Change

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Software & Part Ecosystem

Evaluation Kits 2

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SCP-LT3094-EVALZ

LT3094 Signal Chain Evaluation Board | 500mA Ultra Low Noise Negative LDO

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SCP-LT3094-EVALZ

LT3094 Signal Chain Evaluation Board | 500mA Ultra Low Noise Negative LDO

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SCP-LT3094-EVALZ
LT3094 Signal Chain Evaluation Board | 500mA Ultra Low Noise Negative LDO
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Product Detail

Demonstration circuit SCP-LT3094-EVALZ features the LT3094, an ultralow noise, ultrahigh power supply rejection ratio (PSRR) negative low dropout (LDO) regulator. The board operates over an input range of –3.8V to –20V, and can deliver up to 500mA output current.

Like all boards in the Signal Chain Power series, this board is designed to be easily plugged into other SCP boards to form a complete signal chain power system, enabling fast evaluation of low power signal chains. To evaluate this board, some universal SCP hardware is required, namely:

  • SCP-INPUT-EVALZ
  • SCP-OUTPUT-EVALZ
  • SCP-1X5BKOUT-EVALZ
  • SCP-THRUBRD-EVALZ
  • SCP-FILTER-EVALZ
  • SCP-1X2BKOUT-EVALZ
  • SCP-5X1-EVALZ

 

To properly evaluate SCP series demo boards, you will need the SCP Configurator companion software. SCP Configurator can help you choose the right board and topology for your design.

Note that the Demo Manual does not cover details important to the operation and configuration regarding the LT3094. Please refer to the LT3094 data sheet for a complete description of the part.

Resources

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SCP-LT3094-EVALZ - Demo Manual (Rev.0) Download

1.6 M

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SCP-LT3094-EVALZ - Schematic Download

56.69 K

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SCP-LT3094-EVALZ - Design Files Download

3.01 M

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DC2624A

LT3094 Demo Board | Ultralow Noise, Ultrahigh PSRR Negative RF LDO, −20V ≤ VIN ≤ −3.8V, VOUT = −3.3V@500mA

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DC2624A

LT3094 Demo Board | Ultralow Noise, Ultrahigh PSRR Negative RF LDO, −20V ≤ VIN ≤ −3.8V, VOUT = −3.3V@500mA

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DC2624A
LT3094 Demo Board | Ultralow Noise, Ultrahigh PSRR Negative RF LDO, −20V ≤ VIN ≤ −3.8V, VOUT = −3.3V@500mA
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Product Detail

Demonstration circuit 2624A features the LT3094, an ultralow noise, ultrahigh power supply rejection ratio (PSRR) negative low dropout (LDO) regulator. DC2624A operates over an input range of –3.8V to –20V, and can deliver up to 500mA output current. It features ultralow noise (0.8µVRMS from 10Hz to 100kHz) and very high PSRR (75dB at 1MHz).

The LT3094 enable function (EN/UVLO pin) is bidirectional and can be controlled with either a positive or a negative voltage. The LT3094 also offers programmable current limit functionality by connecting a resistor from ILIM to GND. Current monitoring is also achieved by sensing the ILIM pin voltage. The VIOC tracking function controls an upstream switching converter to maintain a constant voltage across the regulator and, hence, minimize power dissipation. The power good feedback (PGFB) pin is used to set a programmable power good threshold, and activates the fast start-up circuitry. To use the power good function, connect an external voltage source at VEXT. If power good and fast start-up functionality are not needed, tie PGFB to IN.

Built-in protection includes reverse battery protection, reverse current protection, internal current limit with foldback, and thermal limit with hysteresis.

The LT3094 data sheet gives a complete description of the part, operation and applications information. The data sheet must be read in conjunction with this demo manual for demonstration circuit DC2624A. The LT3094 is assembled in 12-lead MSOP and 3mm × 3mm DFN packages with an exposed pad on the bottom-side of the IC. Proper board layout is essential for maximum thermal performance.

Resources

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DC2624A Demo Manual (Rev.A) Download

341.71 K

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DC2624A Schematic Download

49.87 K

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DC2624A Design Files Download

1.09 M

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Evaluation Kits2

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SCP-LT3094-EVALZ

LT3094 Signal Chain Evaluation Board | 500mA Ultra Low Noise Negative LDO
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DC2624A

LT3094 Demo Board | Ultralow Noise, Ultrahigh PSRR Negative RF LDO, −20V ≤ VIN ≤ −3.8V, VOUT = −3.3V@500mA

Tools & Simulations 1

LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.

To launch ready-to-run LTspice demonstration circuits for this part:

Step 1: Download and install LTspice on your computer.

Step 2: Click on the link in the section below to download a demonstration circuit.

Step 3: If LTspice does not automatically open after clicking the link below, you can instead run the simulation by right clicking on the link and selecting “Save Target As.” After saving the file to your computer, start LTspice and open the demonstration circuit by selecting ‘Open’ from the ‘File’ menu.

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LT3094 - LDO Linear Regulators Download

1.81 K

spice tool Lt Spice

LT3094 Demo Circuit - Ultralow Noise, Ultrahigh PSRR Negative LDO Regulator (-20V to -3.3V @ 500mA) Download

2.59 K

Reference Designs 2

Figure 1. CN0577 Simplified Block Diagram

CN0577

Analog Front End and Digital Interface for Serial LVDS SAR ADCs

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CN0577

Analog Front End and Digital Interface for Serial LVDS SAR ADCs

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Analog Front End and Digital Interface for Serial LVDS SAR ADCs

Features and Benefits

  • 18-Bit Resolution, 15 MSPS Data Acquisition System
  • Arbitrary Voltage Inputs Supported
  • All Clocking and Power Requirements are Onboard
  • FMC Connector for FPGA Interfacing
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Part Used 8

LTC2387-18 reference design link

ADR4520 reference design link

LT3080 reference design link

ADA4945-1 reference design link

LT3094 reference design link

ADN4661 reference design link

LT1931 reference design link

ADG3241 reference design link

Design & Integration Tools

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CN0577 Design Files link icon

6.81 M

Figure 1. CN0585 Simplified Block Diagram

CN0585

Quad Channel, Low Latency, Data Acquisition and Signal Generation Module

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Quad Channel, Low Latency, Data Acquisition and Signal Generation Module

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Circuits from the lab

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Quad Channel, Low Latency, Data Acquisition and Signal Generation Module

Features and Benefits

  • 4 Analog Input Channels with Configurable Voltage Ranges
  • 4 Analog Output Channels with Configurable Voltage Ranges
  • 200 ns Latency between ADC Measurement and DAC Settling
  • Analog Front End Interface Connector
  • Modeling and Simulation Compatible with MATLAB and Python
  • FMC Connector Interface to FPGA
View Detailed Reference Design external link

Part Used 15

AD3552R reference design link

ADAQ23876 reference design link

AD8541 reference design link

ADP223 reference design link

ADR4525 reference design link

LT3032 Series reference design link

LT3045 reference design link

LT3094 reference design link

LTM8049 reference design link

LTM8074 reference design link

LTM8078 reference design link

LTC6655 reference design link

MAX20333 reference design link

MAX7301 reference design link

MAX77958 reference design link

Resources

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AD3552R Linux Driver link icon

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ADAQ23876 Linux Driver link icon

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CN0585 Design Files link icon

32.13 M

Reference Designs2

Figure 1. CN0577 Simplified Block Diagram

CN0577

Analog Front End and Digital Interface for Serial LVDS SAR ADCs

Figure 1. CN0585 Simplified Block Diagram

CN0585

Quad Channel, Low Latency, Data Acquisition and Signal Generation Module

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