Features and Benefits
- High instantaneous dynamic range
- Noise figure (NF) as low as 13 dB
- Noise spectral density (NSD) as low as −159 dBFS/Hz
- IIP3 up to 36.9 dBm with spurious tones <−99 dBFS
- Tunable band-pass Σ-Δ analog-to-digital converter (ADC)
- 20 MHz to 160 MHz signal bandwidth
- 70 MHz to 450 MHz IF center frequency
- Configurable input full-scale level of −2 dBm to −14 dBm
- Easy to drive resistive IF input
- Gain flatness of 1 dB with under 0.5 dB out-of-band peaking
- Alias rejection greater than 50 dB
- 2.0 GSPS to 3.2 GSPS ADC clock rate
- On-chip PLL clock multiplier
- 16-bit I/Q rate up to 266 MSPS
- On-chip digital signal processing
- NCO and quadrature digital downconverter (QDDC)
- Selectable decimation factor of 12, 16, 24, and 32
- Automatic gain control (AGC) support
- On-chip attenuator with 27 dB span in 1 dB steps
- Fast attenuator control via configurable AGC data port
- Peak detection flags with programmable thresholds
- Single or dual lane, JESD204B capable
- Low power consumption: 1.20 W
- 1.1 V and 2.5 V supply voltage
- TDD power saving up to 60%
- 4.3 mm × 5.0 mm WLCSP
For a limited time, take a live test drive of the AD6676 by using our remote evaluation software.
The AD6676 is a highly integrated IF subsystem that can digitize radio frequency (RF) bands up to 160 MHz in width centered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, the AD6676 relies on a tunable band-pass Σ-Δ ADC with a high oversampling ratio to eliminate the need for band specific IF SAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadrature digital downconversion followed by selectable decimation filters reduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interface supporting line rates of up to 5.333 Gbps.
- Wideband cellular infrastructure equipment and repeaters
- Point-to-point microwave equipment
- Spectrum and communication analyzers
- Software defined radio
Markets and Technologies
Sample orders for small quantities may be coordinated by contacting email@example.com.
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
The AD6676EBZ supports the AD6676 highly integrated IF subsystem that can digitize radio frequency (RF) bands up to 160 MHz in width centered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, the AD6676 relies on a tunable band-pass Σ-Δ ADC with a high oversampling ratio to eliminate the need for band specific IF SAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadrature digital downconversion followed by selectable decimation filters reduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interface supporting line rates up to 5.333 Gbps.
The AD6676EBZ is compatible with the HSC-ADC-EVALEZ, the ADI FPGA-Based Data Capture Kit.
Documentation & Resources
JESD204 Serial Interface2/14/2015
AD6676 High-speed Broadband IF Receiver4/18/2019
High Dynamic Range Wideband Receiver11/28/2018
Complete 3GHz Signal Analyzer Solution from Analog Devices10/15/2018
Use Noise Spectral Density to Evaluate ADCs in Software-Defined Systems6/1/2017
Bandwidth Demands Place New Strains on Satellite Communications Design2/1/2016
A Wideband Analog Front End Based on a Continuous Time, ∆-Σ High Speed ADC Reduces Power Consumption of High Performance Communication and Instrumentation Systems3/1/2015
High Dynamic Range IF Receiver Simplifies Design of Next-Generation μW Point-to-Point Modems11/1/2014
Software & Systems Requirements
JESD204 Interface Framework
Tools & Simulations
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
AD6676 Companion Parts
Recommended Power Regulator Solutions
- For dual regulator solution supporting the 2.5 V analog and 1.8-2.5 V SPI Interface supplies: ADP223.
- For a high accuracy, low noise 1.1 V supply solution: ADP1752.
Recommended RF Mixers
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
|Part Number||Material Declaration||Reliability Data||Pin/Package Drawing||CAD Symbols, Footprints & 3D Models|
|AD6676BCBZRL||Material Declaration||Reliability Data||80-Ball WLCSP (4.29mm x 5.04mm)|
|Wafer Fabrication Data|
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.