AD6676

RECOMMENDED FOR NEW DESIGNS

AD6676

Wideband IF Receiver Subsystem

RECOMMENDED FOR NEW DESIGNS

RECOMMENDED FOR NEW DESIGNS

AD6676 Functional Block Diagram slide

AD6676 Pin Configuration slide

AD6676 Functional Block Diagram

AD6676 Pin Configuration

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Part Models 1

1ku List Price Starting From $186.18

Features

High instantaneous dynamic range
- Noise figure (NF) as low as 13 dB
- Noise spectral density (NSD) as low as −159 dBFS/Hz
- IIP3 up to 36.9 dBm with spurious tones <−99 dBFS
Tunable band-pass Σ-Δ analog-to-digital converter (ADC)
- 20 MHz to 160 MHz signal bandwidth
- 70 MHz to 450 MHz IF center frequency
- Configurable input full-scale level of −2 dBm to −14 dBm
  - Easy to drive resistive IF input
- Gain flatness of 1 dB with under 0.5 dB out-of-band peaking
  - Alias rejection greater than 50 dB
- 2.0 GSPS to 3.2 GSPS ADC clock rate
  - On-chip PLL clock multiplier
- 16-bit I/Q rate up to 266 MSPS
On-chip digital signal processing
- NCO and quadrature digital downconverter (QDDC)
- Selectable decimation factor of 12, 16, 24, and 32
Automatic gain control (AGC) support
- On-chip attenuator with 27 dB span in 1 dB steps
- Fast attenuator control via configurable AGC data port
- Peak detection flags with programmable thresholds
Single or dual lane, JESD204B capable
Low power consumption: 1.20 W
- 1.1 V and 2.5 V supply voltage
- TDD power saving up to 60%
4.3 mm × 5.0 mm WLCSP

Additional Details

The AD6676 is a highly integrated IF subsystem that can digitize radio frequency (RF) bands up to 160 MHz in width centered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, the AD6676 relies on a tunable band-pass Σ-Δ ADC with a high oversampling ratio to eliminate the need for band specific IF SAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadrature digital downconversion followed by selectable decimation filters reduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interface supporting line rates of up to 5.333 Gbps.

Applications

Wideband cellular infrastructure equipment and repeaters
Point-to-point microwave equipment
Instrumentation
- Spectrum and communication analyzers
Software defined radio

Sample orders for small quantities may be coordinated by contacting highspeed.converters@analog.com.

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FAQs

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Part Models 1

1ku List Price Starting From $186.18

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Technical Documents 7

AD6676: Wideband IF Receiver Subsystem Data Sheet (Rev.D) 09/30/2015

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AD6676: Design Tools And Startup Guide For The Ad6676 Evaluation Board, A High Dynamic Range, Wideband Receiver 03/12/2015

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A Wideband Analog Front End Based on a Continuous Time, ∆-Σ High Speed ADC Reduces Power Consumption of High Performance Communication and Instrumentation Systems 03/01/2015

High Dynamic Range IF Receiver Simplifies Design of Next-Generation μW Point-to-Point Modems 11/01/2014

Bandwidth Demands Place New Strains on Satellite Communications Design 02/01/2016

Use Noise Spectral Density to Evaluate ADCs in Software-Defined Systems 06/01/2017

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JESD204 Serial Interface 02/14/2015

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Reference Materials 10

AD6676 GitHub no-OS Driver Source Code 08/06/2024

AD6676 Linux GitHub Driver Source Code 08/18/2024

Altera AN-753 (AD6676 Arria10) 11/02/2015

Validating ADI Converters Inter-operability with Xilinx FPGA and JESD204B/C IP 04/10/2017

GSPS DACs Enable Ultra-Wide Bandwidth Applications 01/26/2016

Conquering Your Electronic Countermeasures and Surveillance Design Challenges 07/19/2016

Simplifying Radio Design Using a Wideband IF Receiver Subsystem IC 03/02/2015

Video

3

Thumbnail Image

Video

2014-11-06

02:41

AD6676 High-speed Broadband IF Receiver

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Thumbnail Image

Video

2016-06-13

01:18

Complete 3GHz Signal Analyzer Solution from Analog Devices

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Video

2015-06-05

01:34

High Dynamic Range Wideband Receiver

Learn More

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Design Resources 1

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.

Part Model	Pin/Package Drawing	Documentation	CAD Symbols, Footprints, and 3D Models
AD6676BCBZRL	80-Ball WLCSP (4.29mm x 5.04mm)	HTML Material Declaration HTML Reliablity Data	Ultra Librarian SamacSys

AD6676BCBZRL
Pin/Package Drawing
80-Ball WLCSP (4.29mm x 5.04mm)
Documentation

HTML Material Declaration

external-link

HTML Reliablity Data

external-link

CAD Symbols, Footprints, and 3D Models
Ultra Librarian
SamacSys

PCN/PDN Information

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Part Models

Product Lifecycle

PCN

Mar 13, 2018

- 18_0042

AD6676 Assembly Bumping Site Transfer from Amkor to TSMC

AD6676BCBZRL

PRODUCTION

pdf

PCN18_0042_Form

xls

Material_Report

Qualification Results Summary

Filter by Model

Part Models

Product Lifecycle

PCN

Mar 13, 2018

- 18_0042

AD6676 Assembly Bumping Site Transfer from Amkor to TSMC

AD6676BCBZRL

PRODUCTION

pdf

PCN18_0042_Form

xls

Material_Report

Qualification Results Summary

Software 2

AD6676 GitHub no-OS Driver Source Code NEW

AD6676 Linux GitHub Driver Source Code NEW

View Evaluation Software

external link

Companion Parts 7

Parts	Product Life Cycle	Description
Fractional-N PLL1
ADF4355-2	RECOMMENDED FOR NEW DESIGNS	Microwave Wideband Synthesizer with Integrated VCO
Gain Blocks2
ADL5541	PRODUCTION	20 MHz to 6 GHz RF/IF Gain Block, Fixed Gain of 15 dB
ADL5542	PRODUCTION	20 MHz to 6 GHz RF/IF Gain Block, Fixed Gain of 20 dB
Positive Linear Regulators (LDO)2
ADP223	RECOMMENDED FOR NEW DESIGNS	Dual, 300 mA Adjustable Output, Low Noise, High PSRR Voltage Regulator
ADP1752	PRODUCTION	800mA Low-Vin LDO Regulator
RF Mixers with Integrated LO1
ADRF6620	Obsolete	700 MHz to 2700 MHz RX Mixer with Integrated IF DGA, Fractional-N PLL, and VCO
Single, Double, and Triple Balanced Mixers1
ADL5801	RECOMMENDED FOR NEW DESIGNS	High IP3, 10 MHz TO 6 GHz, Active Mixer

Evaluation Software 2

The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.

HTML JESD204x Frame Mapping Table Generator

Integrated JESD204 software framework for rapid system-level development and optimization

HTML JESD204 Interface Framework

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EVAL-AD6676

AD6676 Evaluation Board

EVAL-AD6676

AD6676 Evaluation Board

Buy Now View Details

Product Detail

The AD6676EBZ supports the AD6676 highly integrated IF subsystem that can digitize radio frequency (RF) bands up to 160 MHz in width centered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, the AD6676 relies on a tunable band-pass Σ-Δ ADC with a high oversampling ratio to eliminate the need for band specific IF SAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadrature digital downconversion followed by selectable decimation filters reduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interface supporting line rates up to 5.333 Gbps.

The AD6676EBZ is compatible with the HSC-ADC-EVALEZ, the ADI FPGA-Based Data Capture Kit.

Resources

WIKI

AD6676: Design Tools And Startup Guide For The Ad6676 Evaluation Board, A High Dynamic Range, Wideband Receiver

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evaluation kit item images

EVAL-AD6676

AD6676 Evaluation Board

IBIS Model 1

AD6676 AMI Model

ADC Companion Transport Layer RTL Code Generator Tool

ADC Companion Transport Layer RTL Code Generator Tool

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

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