Features and Benefits

  • High instantaneous dynamic range
    • Noise figure (NF) as low as 13 dB
    • Noise spectral density (NSD) as low as −159 dBFS/Hz
    • IIP3 up to 36.9 dBm with spurious tones <−99 dBFS
  • Tunable band-pass Σ-Δ analog-to-digital converter (ADC)
    • 20 MHz to 160 MHz signal bandwidth
    • 70 MHz to 450 MHz IF center frequency
    • Configurable input full-scale level of −2 dBm to −14 dBm
      • Easy to drive resistive IF input
    • Gain flatness of 1 dB with under 0.5 dB out-of-band peaking
      • Alias rejection greater than 50 dB
    • 2.0 GSPS to 3.2 GSPS ADC clock rate
      • On-chip PLL clock multiplier
    • 16-bit I/Q rate up to 266 MSPS
  • On-chip digital signal processing
    • NCO and quadrature digital downconverter (QDDC)
    • Selectable decimation factor of 12, 16, 24, and 32
  • Automatic gain control (AGC) support
    • On-chip attenuator with 27 dB span in 1 dB steps
    • Fast attenuator control via configurable AGC data port 
    • Peak detection flags with programmable thresholds
  • Single or dual lane, JESD204B capable
  • Low power consumption: 1.20 W
    • 1.1 V and 2.5 V supply voltage
    • TDD power saving up to 60%
  • 4.3 mm × 5.0 mm WLCSP

Product Details

For a limited time, take a live test drive of the AD6676 by using our remote evaluation software.

The AD6676 is a highly integrated IF subsystem that can digitize radio frequency (RF) bands up to 160 MHz in width centered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, the AD6676 relies on a tunable band-pass Σ-Δ ADC with a high oversampling ratio to eliminate the need for band specific IF SAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadrature digital downconversion followed by selectable decimation filters reduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interface supporting line rates of up to 5.333 Gbps.


  • Wideband cellular infrastructure equipment and repeaters 
  • Point-to-point microwave equipment 
  • Instrumentation 
    • Spectrum and communication analyzers 
  • Software defined radio

Sample orders for small quantities may be coordinated by contacting highspeed.converters@analog.com.

Product Lifecycle icon-recommended Recommended for New Designs

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

Evaluation Kits (1)

Software & Systems Requirements

Evaluation Software

JESD204 Interface Framework

Integrated JESD204 software framework for rapid system-level development and optimization

Tools & Simulations

Design Tools

Companion Transport Layer RTL Code Generator Tool (Rev. 1.0)

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

JESD204x Frame Mapping Table Generator

The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.

Product Recommendations

AD6676 Companion Parts

Recommended Power Regulator Solutions

  • For a high accuracy, low noise 1.1 V supply solution: ADP1752.
  • For dual regulator solution supporting the 2.5 V analog and 1.8-2.5 V SPI Interface supplies: ADP223.

Recommended RF Mixers

  • For a 0.7 to 2.7 GHz Rx mixer with integrated LO: ADRF6620.
  • For a 10 MHz to 6 GHz active Rx mixer: ADL5801.

Recommended Amplifer Solution

  • For VHF applications requiring a low noise, high dynamic range gain block: ADL5541, ADL5542.

Recommended Clocking Solutions

  • For a low phase noise external RF clock source: ADF4355-2.

Design Resources

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

PCN-PDN Information

Sample & Buy

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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.