AD9081
Info : RECOMMENDED FOR NEW DESIGNS
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AD9081

MxFE™ Quad, 16-Bit, 12GSPS RFDAC and Quad, 12-Bit, 4GSPS RFADC

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 4
1ku List Price Starting From $1177.00
Features
  • Flexible, reconfigurable common platform design
    • 4 DACs and 4 ADCs (4D4A)
    • Supports single, dual, and quad band
    • Datapaths and DSP blocks are fully bypassable
    • DAC to ADC sample rate ratios of 1, 2, 3, and 4
    • On-chip PLL with multichip synchronization
      • External RFCLK input option for off-chip PLL
  • Maximum DAC sample rate up to 12 GSPS
    • Maximum data rate up to 12 GSPS using JESD204C
    • Useable analog bandwidth to 8 GHz
  • Maximum ADC sample rate up to 4 GSPS
    • Maximum data rate up to 4 GSPS using JESD204C
    • 7.5 GHz analog input full power bandwidth (−3 dB)
  • ADC ac performance at 4 GSPS, input at −2.7 GHz, −1 dBFS
    • Full-scale input voltage: 1.4 V p-p
    • Noise density: −147.5 dBFS/Hz
    • Noise figure: 26.8 dB
    • HD2: −67 dBFS
    • HD3: −73 dBFS
    • Worst other (excluding HD2 and HD3): −79 dBFS at 2.7 GHz
  • DAC ac performance at 12 GSPS
    • Full-scale output current range: 6.43 mA to 37.75 mA
    • Two-tone IMD3 (−7 dBFS per tone): −78.9 dBc
    • NSD, single-tone at 3.7 GHz: −155.1 dBc/Hz
    • SFDR, single-tone at 3.7 GHz: −70 dBc
  • SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps
    • 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver Rx (JRx)
    • JESD204B compliance with the maximum 15.5 Gbps
    • JESD204C compliance with the maximum 24.75 Gbps
    • Supports real or complex digital data (8-, 12-, 16-, or 24-bit)
  • Versatile digital features
    • Configurable or by-passable DDCs and DUCs
      • 8 fine complex DUCs and 4 coarse complex DUCs
      • 8 fine complex DDCs and 4 coarse complex DDCs
      • 48-bit NCO per DUC or DDC
    • Programmable 192-tap PFIR filter for receive equalization
      • Supports 4 different profile settings loaded via GPIO
    • Programmable delay per datapath
    • Receive AGC support
      • Fast detect with low latency for fast AGC control
      • Signal monitor for slow AGC control
    • Transmit DPD support
      • Fine DUC channel gain control and delay adjust
      • Coarse DDC delay adjust for DPD observation path
  • Auxiliary features
    • Fast frequency hopping and direct digital synthesis (DDS)
    • Low latency loopback mode (receive datapath data can be routed to the transmit datapaths)
    • ADC clock driver with selectable divide ratios
    • Power amplifier downstream protection circuitry
    • On-chip temperature monitoring unit
    • Flexible GPIO pins
    • TDD power savings option and sharing ADCs
  • 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch
Additional Details
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The AD9081 mixed signal front end (MxFE®) is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. The AD9081 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) that have wide instantaneous bandwidth. The device features eight transmit and eight receive lanes that support 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B standards. The device also has an on-chip clock multiplier, and a digital signal processing (DSP) capability targeted at either wideband or multiband direct to RF applications. The DSP datapaths can be bypassed to allow a direct connection between the converter cores and the JESD204 data transceiver port. The device also features low latency loopback and frequency hopping modes targeted at phase array radar system and electronic warfare applications. Two models for the AD9081 are offered. The 4D4AC model supports the full instantaneous channel bandwidth, whereas the 4D4AB model supports a maximum instantaneous bandwidth of 600 MHz per channel by automatically configuring the DSP to limit the instantaneous bandwidth at startup.

APPLICATIONS

  • Wireless communications infrastructure
  • Microwave point-to-point, E-band and 5G mmWave
  • Broadband communications systems
  • DOCSIS 3.1 and 4.0 CMTS
  • Phased array radar and electronic warfare
  • Electronic test and measurement systems
Part Models 4
1ku List Price Starting From $1177.00

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Documentation

Documentation

Video

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9081BBPZ-4D4AB
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AD9081BBPZ-4D4AC
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AD9081BBPZRL-4D4AB
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AD9081BBPZRL-4D4AC
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Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 4

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QUAD-MxFE Platform

16Tx/16Rx Direct L/S/C-Band Sampled Phased-Array/RADAR/EW/SATCOM Development Platform

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QUAD-MxFE Platform

16Tx/16Rx Direct L/S/C-Band Sampled Phased-Array/RADAR/EW/SATCOM Development Platform

16Tx/16Rx Direct L/S/C-Band Sampled Phased-Array/RADAR/EW/SATCOM Development Platform

Features and Benefits

Quad-MxFE Digitizing Card
  • Multi-Channel, Wideband System Development Platform Using MxFE
  • Mates With Xilinx VCU118 Evaluation Board (Not Included)
  • 16x RF Receive (Rx) Channels (32x Digital Rx Channels)
    • Total 16x 1.5GSPS to 4GSPS ADC
    • 48x Digital Down Converters (DDCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
    • 16x Programmable Finite Impulse Response Filters (pFIRs)
  • 16x RF Transmit (Tx) Channels (32x Digital Tx Channels)
    • Total 16x 3GSPS to 12GSPS DAC
    • 48x Digital Up Converters (DUCs) , Each Including Complex Numerically-Controlled Oscillators (NCOs)
  • Flexible Rx & Tx RF Front-Ends
    • Rx: Filtering, Amplification, Digital Step Attenuation for Gain Control
    • Tx: Filtering, Amplification
  • On-Board Power Regulation from Single 12V Power Adapter (Included)
  • Flexible Clock Distribution
    • On-Board Clock Distribution from Single External 500MHz Reference
    • Support for External Converter Clock per MxFE
16Tx / 16Rx Calibration Board
  • Mates to Quad-MxFE Digitizing Card & VCU118 PMOD Interface (Cable Included)
  • Provides Both Individual Adjacent Channel Loopback and Combined Channel Loopback Options
  • Combined Tx Channels Out Via SMA Option
  • Combined Rx Channels In Via SMA Option
  • On-Board Log Power Detectors With AD5592R Output To VCU118 Over PMOD
  • On-Board Power Regulation from Single 12V Power Adapter (Included)
Software Features and Benefits
Easy Control Tools and Platform Interfaces to Simplify Software Framework Developments:
  • IIO Oscilloscope GUI
  • MATLAB Add-Ons & Example Scripts
  • Example HDL Builds including JESD204b/JESD204c Bring-Up
  • Embedded Software Solutions for Linux and Device Drivers
  • MATLAB System Applications GUI
Software Reference Design Examples for ADEF Applications to Reduce Prototyping Time:
  • Multi-Chip Synchronization for Power-Up Phase Determinism
  • System-Level Amplitude/Phase Alignment Using NCOs
  • Low-Latency ADC-to-DAC Loopback Bypassing JESD Interface
  • pFIR Control for Broadband Channel-to-Channel Amplitude/Phase Alignment
  • Fast-Frequency Hopping
  • Calibration Board MATLAB Driver File
  • FPGA Programming MATLAB Script

Product Detail

The Quad-MxFE System Development Platform contains four MxFE software defined, direct RF sampling transceivers, as well as associated RF front-ends, clocking, and power circuitry. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a 16 transmit/16 receive channel direct sampling phased array at L/S/C band (0.1 GHz to ~5GHz). The Rx & Tx RF front-end has drop-in configurations that allow for customized frequency ranges, depending on the user’s application.

The Quad-MxFE System Development Platform highlights a complete system solution. It is intended as a testbed for demonstrating multi-chip synchronization as well as the implementation of system level calibrations, beamforming algorithms, and other signal processing algorithms. The system is designed to mate with a VCU118 Evaluation Board from Xilinx®, which features the Virtex® UltraScale+ XCVU9P FPGA, with provided reference software, HDL code, and MATLAB system-level interfacing.

In addition to the Quad-MxFE Digitizing Card, the kit also contains a 16Tx / 16Rx Calibration Board that is used to develop system-level calibration algorithms, or otherwise more easily demonstrate power-up phase determinism in situations pertinent to their own use case. The Calibration Board also allows the user to demonstrate combined-channel dynamic range, spurious, and phase noise improvements and can also be controlled via a free MATLAB add-on when connected to the PMOD interface of the VCU118.

The system can be used to enable quick time-to-market development programs for applications like:

  • ADEF (Phased-Array, RADAR, EW, SATCOM)
  • Communications Infrastructure (Multiband 5G and mmWave 5G)
  • Electronic Test and Measurement
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EVAL-AD9081

AD9081 Evaluation Board

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EVAL-AD9081

AD9081 Evaluation Board

AD9081 Evaluation Board

Features and Benefits

  • Fully functional evaluation boards for the AD9081
  • PC software for control with ACE software
  • On-board clocking provided by the HMC7044 manages device and FPGA clocking
  • Option to switch to external direct clocking

Product Detail

The AD9081-FMCA-EBZ evaluation board includes all of the support circuitry required to operate the AD9081 in various modes and configurations. The application software used to interface with the device is also described. The AD9081-FMCA-EBZ evaluation board connects to the Analog Devices, Inc., ADS9-V2EBZ for evaluation with the ACE software. The boards can also interface to commercially available field-programmable gate array (FPGA) development boards from Xilinx® or Intel®. Information on how to use these platforms to evaluate the AD9081 or AD9082 is available in the Using the AD-FMC-SDCARD section.

The ACE software allows the user to set up the AD9081 or AD9082 in various modes, and capture analog-to-digital converter (ADC) data for analysis. The DPGDownloaderLite software generates and transmits vectors to the DACs, which can then be sent to a spectrum analyzer for further analysis. For more details, see the AD9081 and AD9082 data sheets, which must be consulted in conjunction with this user guide when using the evaluation boards.

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ADS9-V2EBZ

ADS9-V2EBZ Evaluation Board

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ADS9-V2EBZ

ADS9-V2EBZ Evaluation Board

ADS9-V2EBZ Evaluation Board

Features and Benefits

Xilinx Kintex Ultrascale+ XCKU15P-2FFVE1517E FPGA.

  • One (1) FMC+ connector.
  • Twenty (20) 28Gbps transceivers supported by one (1) FMC+ connector.
  • HMC DRAM
  • Simple USB 3.0 port interface.
  • Two micro SD cards are included, "TRX" -- for ADRV9026 evaluation boards and "HSX" -- for MxFE evaluation boards.

Product Detail

When connected to a specified Analog Devices high speed converter evaluation board, the ADS9-V2EBZ works as a data capture/transmit board. Designed to support the highest speed JESD204B/C data converters, the FPGA on the ADS9-V2EBZ acts as the data receiver for high speed ADC's, and as the transmitter for high speed DAC's.
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X-Band Phased Array Platform

Scalable 32 Element Hybrid Beamforming Phased-Array RADAR Development Platform

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X-Band Phased Array Platform

Scalable 32 Element Hybrid Beamforming Phased-Array RADAR Development Platform

Scalable 32 Element Hybrid Beamforming Phased-Array RADAR Development Platform

Features and Benefits

Stingray X/Ku Phased Array Proto-typing Board
  • 32 Channel Analog Phased Array Prototyping Platform
  • 8x ADAR1000 Analog Phased Array Beamforming ICs
  • 32x ADTR Transmit/Receive ICs
  • RF In, RF Out Design
  • Individual RFIO for each BFIC
  • 10 GHz Lattice Spacing
  • Stand-Alone RF Detector/ADC Combo for Calibration
  • PMOD and SDP Connectors for Programming
  • On-Board Power Regulation from Single 12V Power Adapter (Included)

XUD1A X/C Band Up/Down Converter
  • X Band (RF) to C Band (IF) up/down converter
  • 4 TX/RX RF Input/Output via SMA
  • 4 TX IF Inputs via SMPM
  • 4 RX IF Output via SMPM
  • External LO or Internal PLL Options
  • PMOD Connector for Programming
  • Interposer Board via PMOD to allow SDP and FMC Connectors for Programming
  • On-Board Power Regulation from Single 12V Power Adapter (Included)

MxFE Evaluation Board
  • Mates with Xilinx ZCU102 Evaluation Board (Not Included)
  • 4x RF Receive (Rx) Channels (8x Digital Rx Channels)
    • Total 4x 12-bit 4GSPS ADC
    • 8x Digital Down Converters (DDCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
    • 8x Programmable Finite Impulse Response Filters (pFIRs)
  • 4x RF Transmit (Tx) Channels (8x Digital Tx Channels)
    • Total 4x 16-bit 12GSPS DAC
    • 8x Digital Up Converters (DUCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
  • Flexible Clock Distribution
    • On-Board Clock Distribution from Single External 500MHz Reference
    • Support for External Converter Clock
  • On-Board Power Regulation Powered by ZCU102 Evaluation Board via FMC Connector

Software Features and Benefits
Easy Control Tools and Platform Interfaces to Simplify Software Framework Developments:
  • MATLAB System Applications GUI
  • Example HDL Builds including JESD204b/JESD204c Bring-Up
  • Embedded Software Solutions for Linux and Device Drivers

Software Reference Design Examples for ADEF Applications to Reduce Prototyping Time:
  • Hybrid Beamsteering Capability
  • System Phase Calibration

Product Detail

The X-Band Development Platform contains one MxFE® software defined, direct RF sampling transceivers, X-Band to C-Band Up/Down Converter, and a X/Ku Band analog phased array proto-typing platform. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a X Band 32 transmit/32 receive channel hybrid beamforming phased array radar.

The X-Band Development Platform highlights a complete system solution. It is intended as a testbed for demonstrating hybrid beamforming phased array radar as well as the implementation of system level calibrations, beamforming algorithms, and other signal processing algorithms. The system is designed to mate with a ZCU102 Evaluation Board from Xilinx®, which features the Zynq® UltraScale+ MPSoC FPGA, with provided reference software, HDL code, and MATLAB system-level interfacing software.

The system can be used to enable quick time-to-market development programs for applications like:

  • ADEF (Phased-Array, RADAR, EW, SATCOM)
  • Hybrid Beamforming
  • Electronic Test and Measurement
Tools & Simulations

Tools & Simulations 9

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