Not the part you were looking for?
Ask a Question
Submit your question below and we will return the best answer from ADI’s knowledge database:
Search
Other places you can find help
Support
Analog Devices Support Portal is a one-stop shop to answer all your ADI questions.
Visit the ADI Support Page
Features
- DAC update rate up to 12 GSPS (minimum)
- Direct RF synthesis at 6 GSPS (minimum)
- DC to 3 GHz in nonreturn-to-zero (NRZ) mode
- DC to 6 GHz in 2× NRZ mode
- 1.5 GHz to 7.5 GHz in Mix-Mode
- Selectable interpolation
- 6×, 8×, 12×, 16×, 24×
- Excellent dynamic performance
.svg?rev=fd385c90e2cf4716ae9a8c8d20e6b8e3&la=en&h=24&w=24&hash=A302DF48F94BAAA11877AF223F27157A){kind=icon}
The AD91631 is a high performance, 16-bit digital-to-analog converter (DAC) that supports data rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2× interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes this DAC ideally suited for the most demanding high speed radio frequency (RF) DAC applications.
Superior RF performance and deep interpolation rates enable use of the AD9163 in many wireless infrastructure applications, including MC-GSM, W-CDMA, LTE, and LTE-A.
The wide bandwidth of up to 1 GHz and the complex NCO and digital upconverter enable dual band and triple band direct RF synthesis of wireless infrastructure signals, eliminating costly analog upconverters.
Wide analog bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of one carrier up to 1 GHz of signal bandwidth, making it ideal for cable multiple dwelling unit (MDU) applications. A 2× interpolator filter (FIR85) enables the AD9163 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode™ operation, the AD9163 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9163 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.
A serial peripheral interface (SPI) configures the AD9163 and monitors the status of all the registers. The AD9163 is offered in a 169-ball, 11 mm × 11 mm, 0.8 mm pitch CSP_BGA package.
Product Highlights
- High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz.
- Up to eight lanes JESD204B SERDES interface, flexible in terms of number of lanes and lane speed.
- Bandwidth and dynamic range to meet multiband wireless communications standards with margin.
Applications
- Broadband communications systems
- DOCSIS 3.1 cable modem termination system (CMTS)/ video on demand (VOD)/edge quadrature amplitude modulation (EQAM)
- Wireless communications infrastructure
- MC-GSM, W-CDMA, LTE, LTE-A, point to point
Ask a Question
Submit your question below and we will return the best answer from ADI’s knowledge database:
Search
Other places you can find help
Support
Analog Devices Support Portal is a one-stop shop to answer all your ADI questions.
Visit the ADI Support Page
{{modalTitle}}
{{modalDescription}}
{{dropdownTitle}}
- {{defaultSelectedText}} {{#each projectNames}}
- {{name}} {{/each}} {{#if newProjectText}}
-
{{newProjectText}}
{{/if}}
{{newProjectTitle}}
{{projectNameErrorText}}
AD9163
Documentation
Filters
1 Applied
-
All
-
Data Sheet
-
User Guide
-
All
-
English
Data Sheet
1
User Guide
1
Documentation
Device Drivers 1
FPGA Interoperability Reports 1
Analog Dialogue 1
Webcast 2
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9163BBCZ |
169-Ball CSPBGA (11mm x 11mm x 0.95mm)
|
|
|
| AD9163BBCZRL |
169-Ball CSPBGA (11mm x 11mm x 0.95mm)
|
|
- AD9163BBCZ
- Pin/Package Drawing
-
169-Ball CSPBGA (11mm x 11mm x 0.95mm)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9163BBCZRL
- Pin/Package Drawing
-
169-Ball CSPBGA (11mm x 11mm x 0.95mm)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
Filter by Model
Part Models
Product Lifecycle
PCN
Jan 30, 2020
- 20_0020
AD9161/AD9162/AD9163/AD9164 Die Revision
AD9163BBCZ
PRODUCTION
AD9163BBCZRL
PRODUCTION
Filter by Model
Part Models
Product Lifecycle
PCN
Jan 30, 2020
- 20_0020
AD9161/AD9162/AD9163/AD9164 Die Revision
AD9163BBCZ
PRODUCTION
AD9163BBCZRL
PRODUCTION
Software & Part Ecosystem
Device Drivers
Code Examples
AD916x API
Looking for Evaluation Software? You can find it here
| Parts | Product Life Cycle | Description | ||
|---|---|---|---|---|
|
Clock Distribution Devices1 |
||||
|
LAST TIME BUY |
Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
|||
|
Clock Generation Devices2 |
||||
|
RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
|||
|
LAST TIME BUY |
Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
|||
|
Phase Locked Loop with Integrated VCO1 |
||||
|
RECOMMENDED FOR NEW DESIGNS |
Microwave Wideband Synthesizer with Integrated VCO |
|||
Can't find the software or driver you need?
Request a Driver/SoftwareEvaluation Kits 3
EVAL-AD916X
AD9161/AD9162/AD9163/AD9164 Evaluation Board
Product Detail
This user guide is for the AD9161, AD9162, AD9163, and AD9164 evaluation board. The evaluation board connects to an ADS7-V2EBZ pattern generator for quick evaluation of the AD9161, AD9162, AD9163, and AD9164, high speed, RF digital-to-analog converters (RF DACs). The ADS7-V2EBZ automatically formats the data and sends it to the evaluation board, which simplifies evaluation of the device. The evaluation board runs from the FPGA mezzanine card (FMC) power supply.
The evaluation board includes a clock buffer, the AD9508, which provides the reference clock and SYSREF± pins to the ADS7-V2EBZ, and the SYSREF± pins signal to the DAC.
The evaluation board can be driven by an external clock or the on-board clock (ADF4355). There is a single-pole, double throw (SPDT) switch on the board for selecting the clock source.
Resources
ADS8-V1EBZ
ADS8-V1 Evaluation Board
Product Detail
When connected to a specified Analog Devices high speed adc evaluation board, the ADS8-V1 works as a data acquistion board. Designed to support the highest speed JESD204B A/D Converters, the FPGA on the ADS8-V1 acts as the data receiver, while the ADC is the data transmitter.
Resources
ADS7-V2EBZ
FPGA Based Data Capture Kit
Product Detail
Resources
Tools & Simulations 5
IBIS Model 1
IBIS Model
Using MATLAB with ADS7 and AD916x Eval Boards
ADIsimRF
JESD204x Frame Mapping Table Generator
DAC Companion Transport Layer RTL Code Generator
