AD9164
AD9164
Info :
RECOMMENDED FOR NEW DESIGNS
AD9164
16-Bit, 12 GSPS, RF DAC and Direct Digital Synthesizer
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Info :
RECOMMENDED FOR NEW DESIGNS
Info :
RECOMMENDED FOR NEW DESIGNS
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Part Models
6
1ku List Price
Starting From $378.78
Features
- DAC update rate up to 12 GSPS (minimum)
- Direct RF synthesis at 6 GSPS (minimum)
- DC to 2.5 GHz in baseband mode
- DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode
- 1.5 GHz to 7.5 GHz in Mix-Mode
- Bypassable interpolation
- 2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
- Excellent dynamic performance
- Fast frequency hopping
Additional Details
The AD91641 is a high performance, 16-bit digital-to-analog converter (DAC) and direct digital synthesizer (DDS) that supports update rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2× interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.
The DDS consists of a bank of 32, 32-bit numerically controlled oscillators (NCOs), each with its own phase accumulator.
When combined with a 100 MHz serial peripheral interface (SPI) and fast hop modes, phase coherent fast frequency hopping (FFH) is enabled, with several modes to support multiple applications.
In baseband mode, wide analog bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of one carrier up to the full maximum spectrum of 1.791 GHz of signal bandwidth. A 2× interpolator filter (FIR85) enables the AD9164 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode™ operation, the AD9164 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9164 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.
An SPI interface configures the AD9164 and monitors the status of all registers. The AD9164 is offered in a 165-ball, 8 mm × 8 mm, 0.5 mm pitch CSP_BGA package, and a 169-ball, 11 mm × 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option.
Product Highlights
- High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz.
- Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed.
- Bandwidth and dynamic range to meet DOCSIS 3.1 compliance and multiband wireless communications standards with margin.
Applications
- Broadband communications systems
- DOCSIS 3.1 CMTS/ video on demand (VOD)/edge quadrature amplitude modulation (EQAM)
- Wireless communications infrastructure
- W-CDMA, LTE, LTE-A, point to point
Ask a Question
Submit your question below and we will return the best answer from ADI’s knowledge database:
Other places you can find help
Support
Analog Devices Support Portal is a one-stop shop to answer all your ADI questions.
Visit the ADI Support Page
Part Models
6
1ku List Price
Starting From $378.78
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AD9164
Documentation
2
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Data Sheet
1
User Guide
1
UPDATED 11/08/2019
English
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Documentation
Technical Documents
2
Reference Materials 12
3rd Party Solutions 3
FPGA Interoperability Reports 1
Device Drivers 1
Analog Dialogue 2
Webcast 2
Video
3
Design Resources 6
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
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AD9164BBCA | 169-Ball CSPBGA (11mm x 11mm x 0.95mm) |
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AD9164BBCARL | 169-Ball CSPBGA (11mm x 11mm x 0.95mm) |
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AD9164BBCAZ | 169-Ball CSPBGA (11mm x 11mm x 0.95mm) |
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AD9164BBCAZRL | 169-Ball CSPBGA (11mm x 11mm x 0.95mm) |
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AD9164BBCZ | 165-Ball CSPBGA (8mm x 8mm) |
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AD9164BBCZRL | 165-Ball CSPBGA (8mm x 8mm) |
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- AD9164BBCA
- Pin/Package Drawing
- 169-Ball CSPBGA (11mm x 11mm x 0.95mm)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
- AD9164BBCARL
- Pin/Package Drawing
- 169-Ball CSPBGA (11mm x 11mm x 0.95mm)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
- AD9164BBCAZ
- Pin/Package Drawing
- 169-Ball CSPBGA (11mm x 11mm x 0.95mm)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
- AD9164BBCAZRL
- Pin/Package Drawing
- 169-Ball CSPBGA (11mm x 11mm x 0.95mm)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
- AD9164BBCZ
- Pin/Package Drawing
- 165-Ball CSPBGA (8mm x 8mm)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
- AD9164BBCZRL
- Pin/Package Drawing
- 165-Ball CSPBGA (8mm x 8mm)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
PCN/PDN Information
Filter by Model
Part Models
Product Lifecycle
PCN
Jan 30, 2020
- 20_0020
AD9161/AD9162/AD9163/AD9164 Die Revision
AD9164BBCA
PRODUCTION
AD9164BBCARL
PRODUCTION
AD9164BBCAZ
PRODUCTION
AD9164BBCAZRL
PRODUCTION
AD9164BBCZ
PRODUCTION
AD9164BBCZRL
PRODUCTION
Filter by Model
Part Models
Product Lifecycle
PCN
Jan 30, 2020
- 20_0020
AD9161/AD9162/AD9163/AD9164 Die Revision
AD9164BBCA
PRODUCTION
AD9164BBCARL
PRODUCTION
AD9164BBCAZ
PRODUCTION
AD9164BBCAZRL
PRODUCTION
AD9164BBCZ
PRODUCTION
AD9164BBCZRL
PRODUCTION
Software & Part Ecosystem
Software 2
Device Drivers
Code Examples
AD916x API
Looking for Evaluation Software? You can find it here
Companion Parts 4
Parts | Product Life Cycle | Description | ||
---|---|---|---|---|
Clock Distribution Devices1 |
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LAST TIME BUY |
Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
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Clock Generation Devices2 |
||||
RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
|||
LAST TIME BUY |
Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
|||
Phase Locked Loop with Integrated VCO1 |
||||
RECOMMENDED FOR NEW DESIGNS |
Microwave Wideband Synthesizer with Integrated VCO |
Evaluation Software 1
JESD204x Frame Mapping Table Generator
Info:False
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
Can't find the software or driver you need?
Request a Driver/SoftwareEvaluation Kits 3
EVAL-AD916X
AD9161/AD9162/AD9163/AD9164 Evaluation Board
Product Detail
This user guide is for the AD9161, AD9162, AD9163, and AD9164 evaluation board. The evaluation board connects to an ADS7-V2EBZ pattern generator for quick evaluation of the AD9161, AD9162, AD9163, and AD9164, high speed, RF digital-to-analog converters (RF DACs). The ADS7-V2EBZ automatically formats the data and sends it to the evaluation board, which simplifies evaluation of the device. The evaluation board runs from the FPGA mezzanine card (FMC) power supply.
The evaluation board includes a clock buffer, the AD9508, which provides the reference clock and SYSREF± pins to the ADS7-V2EBZ, and the SYSREF± pins signal to the DAC.
The evaluation board can be driven by an external clock or the on-board clock (ADF4355). There is a single-pole, double throw (SPDT) switch on the board for selecting the clock source.
Resources
ADS8-V1EBZ
ADS8-V1 Evaluation Board
Product Detail
When connected to a specified Analog Devices high speed adc evaluation board, the ADS8-V1 works as a data acquistion board. Designed to support the highest speed JESD204B A/D Converters, the FPGA on the ADS8-V1 acts as the data receiver, while the ADC is the data transmitter.
Resources
ADS7-V2EBZ
FPGA Based Data Capture Kit
Product Detail
The ADS7-V2 Evaluation Board was developed to support the evaluation of Analog Devices high speed A/D converters, D/A converters and Transceivers with JESD204B bit rates up to 13.1 Gbps. The Quick Start Wiki site listed below provides a high level overview of the platform. In addition, each use case of the board has its own section (e.g. Using the ADS7-V2 for High Speed A/D Converter Evaluation). The ADS7-V2 is intended to be used only with specified Analog Devices Evaluation Boards. The ADS7-V2 is not intended to be used as a development platform, and no support is available for standalone operation. Please refer to Xilinx and its approved distributors for FPGA Development Kits
Resources