Features and Benefits
- JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
- Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and 250 MSPS
- Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN and 250 MSPS
- Total power consumption: 434 mW at 250 MSPS
- 1.8 V supply voltages
- Integer 1-to-8 input clock divider
- Sample rates of up to 250 MSPS
- Intermediate frequency (IF) sampling frequencies of up to 400 MHz
- Internal analog-to-digital converter (ADC) voltage reference
- Flexible analog input range: 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
- ADC clock duty cycle stabilizer (DCS)
- Serial port control
- Energy saving power-down modes
The AD9683 is a 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9683 supports communications applications where low cost, small size, wide bandwidth, and versatility are desired. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC core features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device. The ADC output data is routed directly to the JESD204B serial output lane. These outputs are at CML voltage levels. Data can be sent through the lane at the maximum sampling rate of 250 MSPS, which results in a lane rate of 5 Gbps. Synchronization inputs (SYNCINB± and SYSREF±) are provided. Flexible power-down options allow significant power savings, when desired. Programmable overrange level detection is supported via the dedicated fast detect pins. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9683 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
- Integrated 14-bit, 170 MSPS/250 MSPS ADC.
- The configurable JESD204B output block supports lane rates up to 5 Gbps.
- An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock.
- Support for an optional radio frequency (RF) clock input to ease system board design.
- Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz.
- Operation from a single 1.8 V power supply.
- Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, overrange fast detection, and serial output configuration.
- Diversity radio systems
- Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
- Smart antenna systems
- Electronic test and measurement equipment
- Radar receivers
- COMSEC radio architectures
- IED detection/jamming systems
- General-purpose software radios
- Broadband data applications
- Ultrasound equipment
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (2)
The AD9683-250EBZ is an evaluation board for the AD9683, single 14-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations, It is designed to interface directly with the HSC-ADC-EVALEZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9683.
The AD9683 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at High Speed ADC Evaluation Boards page. For additional information or questions, please email firstname.lastname@example.org.
Features & Benefits
- Full featured evaluation board for the AD9683
- SPI interface for setup and control
- External, on-board oscillator, and AD9525 clocking options
- Balun/transformer or amplifier input drive option
- On-board LDO regulator needing a single external 6 V, 2 A dc supply
- VisualAnalog® and SPI controller software interfaces
The HSC-ADC-EVALEZ FMC-Compatible high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up and supports emerging serial interface standards, like JESD204B. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.
Features & Benefits
- 256kB FIFO Depth
- Supports multiple ADC channels via single FMC-HPC interface connector
- JESD-204B support for up to eight (8) 6.5Gbps Lanes
- Parallel input at 644 MSPS SDR and 1.2 GSPS DDR
- Use with VisualAnalog® software
- Based on Virtex-6 FPGA
- Simple USB port interface (2.0)
Documentation & Resources
AN-905: VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual8/18/2020
AN-878: High Speed ADC SPI Control Software (Rev. A)3/20/2018
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)5/12/2015
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)2/14/2015
AN-282: Fundamentals of Sampled Data Systems2/14/2015
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev. 0)2/14/2015
AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0)2/14/2015
AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. C)2/14/2015
AN-345: Grounding for Low-and-High-Frequency Circuits2/14/2015
AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0)2/2/2012
AN-737: How ADIsimADC Models an ADC (Rev. B)11/9/2007
AN-807: Multicarrier WCDMA Feasibility (Rev. 0)11/9/2007
AN-877: Interfacing to High Speed ADCs via SPI (Rev. B)11/9/2007
AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev. 0)7/26/2006
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)11/29/2004
JESD204 Serial Interface2/14/2015
Software & Systems Requirements
JESD204 Interface Framework
Tools & Simulations
AD9683 IBIS Model
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
AD9683 Companion Parts
Recommended Driver Amplifiers
- For a fully differential input and output DVGA in digital communications systems: ADL5201, AD8375.
- For differential RF/IF: ADL5562.
- For DC-coupled inputs: ADA4927-1, ADA4938-1.
Recommended Clock Drivers
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
|Part Number||Material Declaration||Reliability Data||Pin/Package Drawing||CAD Symbols, Footprints & 3D Models|
|AD9683BCPZ-170||Material Declaration||Reliability Data||32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)|
|AD9683BCPZ-250||Material Declaration||Reliability Data||32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)|
|AD9683BCPZRL7-170||Material Declaration||Reliability Data||32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)|
|AD9683BCPZRL7-250||Material Declaration||Reliability Data||32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)|
|Wafer Fabrication Data|
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