JESD204 Interface Framework
Overview
Features and Benefits
Features and Benefits
- System level JESD204 framework designed for faster system integration
- Optimized software package for rapid prototyping and proof-of-concept testing
- HDL code interfaces JESD204 compliant converters and transceivers to FPGAs
- Dynamic configuration capabilities allow for system changes during operation
- Constraint handling supports built-in component models and configures clocks and converters easing system integration
- Commercial and Open Source Licenses available:
GPL-2
- Zero cost, but not public domain
- Unlimited right to run program
- Unlimited access to source code
- Unlimited right to distribute verbatim copies of source
- May create derivatives IF you agree to make the derivatives free and open (distribute your source)
- License is “viral”
- No warranties; disclaimer of consequential damages
- Free EngineerZone support on ADI parts only
Commercial License
- Nominal cost outlined below
- Unlimited use, modification, and distribution
- Can distribute binaries without releasing source code
- Perpetual, multi-project, multi-site
- Must use with ADI devices
- Can sub-license to end users of customer’s product for use on that product only
- No warranties; disclaimer of consequential damages
- Commercial support
- One-on-one phone/email support for 10 hours
- After that, EngineerZone
Additional features:
- Designed to JEDEC JESD204B specification
- Supports 1-256 Octets per frame and 1-32 frames per multi-frame
- Supports 1-32 lane configurations
- Supports line rates up to 12.5Gbps certified to the JESD204B specification
- Supports line rates up to 16.1Gbps
- Provides Physical and Data link layer functions
- AXI4-Stream interface for data
- AXI4-Lite for configuration interface
Product Details
Analog Devices’ JESD204 Interface Framework is a system-level software and HDL package targeted at simplifying system development by providing a performance optimized IP framework that integrates complex hardware such as high speed converters, transceivers and clocks with various FPGA platforms.
The JESD204 Interface Framework provides an open platform that includes dynamic configuration capabilities to allow for system changes during operation and constraint handling to support built-in component models such as clocks and converters. These capabilities improve system-level integration and proof-of-concept testing leading to faster time-to-market.
Direct support is available for Commercial License holders. Contact your local ADI representative.
Markets and Technologies
Compatible Parts
- AD6673
- AD6674
- AD6676
- AD6677
- AD6684
- AD6688
- AD9094
- AD9207
- AD9208
- AD9209
- AD9213
- AD9217
- AD9234
- AD9250
- AD9625
- AD9656
- AD9680
- AD9683
- AD9689
- AD9690
- AD9691
- AD9694
- AD9695
- AD9697
- AD9135
- AD9136
- AD9144
- AD9152
- AD9154
- AD9161
- AD9162
- AD9163
- AD9164
- AD9172
- AD9173
- AD9174
- AD9175
- AD9176
- AD9177
- AD9528
- HMC7043
- HMC7044
- AD9523-1
- AD9081
- AD9082
- AD9371
- AD9375
- AD9986
- AD9988
- ADRV9009
- ADRV9008-1
- ADRV9008-2
Documentation & Resources
-
Synchronizing Sample Clocks of a Data Converter Array6/1/2016
-
JESD204B Survival Guide8/1/2014PDF
-
JESD204 Interface Framework User Guide11/29/2017WIKI