Features and Benefits
- DAC update rate up to 12 GSPS (minimum)
- Direct RF synthesis at 6 GSPS (minimum)
- DC to 2.5 GHz in baseband 1× bypass mode
- DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode
- 1.5 GHz to 7.5 GHz in Mix-Mode
- Bypassable interpolation (1× or bypass mode)
- 2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
- Excellent dynamic performance
The AD9161 is a high performance, 11-bit digital-to-analog converter (DAC) that supports data rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2× interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.
In baseband mode, wide bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of two carriers to full maximum spectrum of 1.794 GHz. A 2× interpolator filter (FIR85) enables the AD9161/AD9162 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode™ operation, the AD9161/AD9162 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9161/AD9162 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.
A serial peripheral interface (SPI) can configure the AD9161/AD9162 and monitor the status of all registers. The AD9161/AD9162 are offered in an 165-ball, 8.0 mm × 8.0 mm, 0.5 mm pitch, CSP_BGA package and in an 169-ball, 11 mm × 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option for the AD9162.
- High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz.
- Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed.
- Bandwidth and dynamic range to meet DOCSIS 3.1 compliance with margin.
- Broadband communications systems
- DOCSIS 3.1 cable modem termination system (CMTS)/video on demand (VOD)/edge quadrature amplitude modulation (EQAM)
- Wireless communications infrastructure
- W-CDMA, LTE, LTE-A, point to point
- Instrumentation, automatic test equipment (ATE)
- Radars and jammers
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (3)
When connected to a specified Analog Devices high speed adc evaluation board, the ADS8-V1 works as a data acquistion board. Designed to support the highest speed JESD204B A/D Converters, the FPGA on the ADS8-V1 acts as the data receiver, while the ADC is the data transmitter.
The ADS7-V2 Evaluation Board was developed to support the evaluation of Analog Devices high speed A/D converters, D/A converters and Transceivers with JESD204B bit rates up to 13.1 Gbps. The Quick Start Wiki site listed below provides a high level overview of the platform. In addition, each use case of the board has its own section (e.g. Using the ADS7-V2 for High Speed A/D Converter Evaluation). The ADS7-V2 is intended to be used only with specified Analog Devices Evaluation Boards. The ADS7-V2 is not intended to be used as a development platform, and no support is available for standalone operation. Please refer to Xilinx and its approved distributors for FPGA Development Kits
This user guide is for the AD9161, AD9162, AD9163, and AD9164 evaluation board. The evaluation board connects to an ADS7-V2EBZ pattern generator for quick evaluation of the AD9161, AD9162, AD9163, and AD9164, high speed, RF digital-to-analog converters (RF DACs). The ADS7-V2EBZ automatically formats the data and sends it to the evaluation board, which simplifies evaluation of the device. The evaluation board runs from the FPGA mezzanine card (FMC) power supply.
The evaluation board includes a clock buffer, the AD9508, which provides the reference clock and SYSREF± pins to the ADS7-V2EBZ, and the SYSREF± pins signal to the DAC.
The evaluation board can be driven by an external clock or the on-board clock (ADF4355). There is a single-pole, double throw (SPDT) switch on the board for selecting the clock source.
Documentation & Resources
RF Converters: A Technology That Is Enabling Wideband Radios3/1/2018
Improved DAC Phase Noise Measurements Enable Ultralow Phase Noise DDS Applications8/1/2017 Analog Dialogue
New RF DAC Broadens Software-Defined Radio Horizon7/1/2016 Analog Dialogue
Software & Systems Requirements
Tools & Simulations
These command line executable tool generates a Verilog module which implements the JESD204 transmitter transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
The AD916x evaluation boards can be used and controlled by a MATLAB simulation. This enables users to verify simulation results by running on actual hardware.
ADIsimDDS uses mathematical equations to model and illustrate the overall performance of the selected device. ADIsimDDS calculates the required FTW, given the reference clock frequency and desired output frequency. This tool also models an estimate of the overall spectral performance, and allows the user to explore the effects of external reconstruction filters.
AD9161 Companion Parts
Recommended Clock Distribution Device
Recommended Clock Generation Device
Recommended PLL with Integrated VCO
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
|Part Number||Material Declaration||Reliability Data||Pin/Package Drawing||CAD Symbols, Footprints & 3D Models|
|AD9161BBCZ||Material Declaration||Reliability Data||169-Ball CSPBGA (11mm x 11mm x 0.95mm)|
|AD9161BBCZRL||Material Declaration||Reliability Data||169-Ball CSPBGA (11mm x 11mm x 0.95mm)|
|Wafer Fabrication Data|
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.