AD9177
RECOMMENDED FOR NEW DESIGNSQuad, 16-Bit, 12 GSPS RF DAC with Wideband Channelizers
- Part Models
- 2
- 1ku List Price
- Starting From $892.77
Part Details
- Flexible reconfigurable common platform design
- 4 DAC cores connected to various DSP and bypass datapaths
- Supports single, dual, and quad band
- Datapaths and DSP blocks are fully bypassable
- On-chip PLL with multichip synchronization
- External RFLK input option for off-chip PLL
- Maximum DAC sample rate up to 12 GSPS
- Maximum data rate up to 12 GSPS using JESD204C
- Useable analog bandwidth to 8 GHz
- DAC ac performance at 12 GSPS
- Full-scale output current range: 6.43 mA to 37.75 mA
- Two tone IMD3 (−7 dBFS per tone): −78.9 dBc
- NSD, single tone at 3.7 GHz: −155.1 dBc/Hz
- SFDR, single tone at 3.7 GHz: −70 dBc
- Versatile digital features
- Selectable interpolation filters
- Configurable or bypassable DUCs
- 8 fine complex DUCs and 4 coarse complex DUCs
- 48-bit NCO per DUC
- Option to bypass fine and coarse DUC
- Programmable delay per datapath
- Transmit DPD support
- Fine DUC channel gain control and delay adjust
- Auxiliary features
- Direct digital synthesis and fast frequency hopping
- Low latency loopback mode (receive datapath NCO outputs can be routed to the transmit datapaths)
- Power amplifier downstream protection circuitry
- On-chip temperature monitoring unit
- Flexible GPIO pins
- TDD power savings option
- SERDES JESD204B/JESD204C interface
- 8-lane JESD204B/C receiver (JRx)
- JESD204B compliance with the maximum 15.5 Gbps
- JESD204C compliance with the maximum 24.75 Gbps
- Supports real or complex digital data (8-, 12-, 16-, or 24-bit)
- 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch
The AD9177 is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores supporting up to eight baseband channels. The device is well suited for applications requiring wideband DACs to process signals of wide instantaneous bandwidth. The device features an 8-lane, 24.75 Gbps JESD204C or 15.5 Gbps JESD204B data receiver (JRx) port, an on-chip clock multiplier, and digital signal processing (DSP) datapaths capable of processing complex signals for wide-band or multiband direct to RF applications, phase array radar systems, and electronic warfare applications. The DSP datapaths can be bypassed to allow a direct connection between the data receiver port and the DAC cores.
For direct digital synthesis (DDS) applications, the AD9177 can be operated without a data receiver port to generate multiple sine wave tones of varying frequencies. The main numerically controlled oscillator (NCO) block inside each of the four course digital upconverters (DUCs) contains one 48-bit NCO and a bank of thirty one 32-bit NCOs, each with an independent phase accumulator. Similarly, the main NCO block inside each of the course and fine digital downconverters (DDCs) in the receive datapath contains a bank of sixteen 48-bit NCOs that can be looped into the transmit datapath for processing ahead of the course DUCs and DAC outputs. Combined with general-purpose input/output (GPIO) controls for frequency hopping, preconfigurable profile selection, and the ability to synchronize the NCOs to a common trigger using the SYSREF input port, this bank allows phase coherent fast frequency hopping (FFH) for applications where multiple devices are synchronized or where NCO frequencies are continuously adjusted during operation.
APPLICATIONS
- Wireless communications infrastructure
- Microwave point-to-point, E-band, and 5G mm wave
- Broadband communications systems
- DOCSIS 3.1 and 4.0 CMTS
- Phased array radar and electronic warfare
- Electronic test and measurement systems
Documentation
Data Sheet 1
User Guide 1
Application Note 1
Design Note 1
Technical Articles 3
FPGA Interoperability Reports 1
Device Drivers 1
Analog Dialogue 2
Video Series 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9177BBPZ | 324-Ball BGA_ED (15mm x 15mm x 1.58mm) | ||
| AD9177BBPZRL | 324-Ball BGA_ED (15mm x 15mm x 1.58mm) |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 1
Evaluation Software 1
JESD204x Frame Mapping Table Generator
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
Can't find the software or driver you need?
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| µModule Buck Regulators 1 | ||
| LTM8053 | RECOMMENDED FOR NEW DESIGNS | 40VIN, 3.5A/6A Step-Down Silent Switcher μModule Regulator |
| Clock Distribution Devices 3 | ||
| HMC7043 | RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C |
| LTC6953 | LAST TIME BUY | Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support |
| LTC6955 | LAST TIME BUY | Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
| Clock Generation Devices 2 | ||
| LTC6952 | LAST TIME BUY | Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
| HMC7044 | RECOMMENDED FOR NEW DESIGNS | High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
| Multiple Output Buck Regulators 3 | ||
| LTM4633 | RECOMMENDED FOR NEW DESIGNS | Triple 10A Step-Down DC/DC μModule (Power Module) Regulator |
|
LTM4644 LTM4644-1 |
Quad DC/DC μModule (Power Module) Regulator with Configurable 4A Output Array | |
| LTM4616 | RECOMMENDED FOR NEW DESIGNS | Dual 8A per Channel Low VIN DC/DC μModule (Power Module) Regulator |
| Phase Locked Loop with Integrated VCO 1 | ||
| ADF4377 | RECOMMENDED FOR NEW DESIGNS | Microwave Wideband Synthesizer with Integrated VCO |
| Positive Linear Regulators (LDO) 4 | ||
| ADP1765 | RECOMMENDED FOR NEW DESIGNS | 5 A, Low VIN, Low Noise, CMOS Linear Regulator |
| ADP7158 | RECOMMENDED FOR NEW DESIGNS | 2 A, Ultralow Noise, High PSRR, Fixed Output, RF Linear Regulator |
| ADM7172 | RECOMMENDED FOR NEW DESIGNS | 6.5 V, 2 A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO |
| ADM7150 | RECOMMENDED FOR NEW DESIGNS | 800 mA, Ultra Low Noise/High PSRR LDO |
| Ultralow Noise Regulators 1 | ||
| LTM8063 | RECOMMENDED FOR NEW DESIGNS | 40VIN, 2A Silent Switcher µModule Regulator |
Tools & Simulations
MxFE JESD204 Mode Selector Tool
The JESD204B/C Mode Selector Tool is a simple command line-based Windows executable that can be used to narrow down the number of JESD204x modes to only include those modes that support the user’s specific application use case. The tool guides the user through a use case description flow chart and gives the user a small list of applicable transmit and/or receive modes to choose from. This tool is applicable to the AD9081, AD9082, AD9177, AD9207, AD9209, AD9986, and AD9988.
Open ToolDAC Companion Transport Layer RTL Code Generator
These command line executable tool generates a Verilog module which implements the JESD204 transmitter transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
Open ToolADIsimPLL™
ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.
Open ToolS-Parameter 2
AD9177 AMI Model
Open ToolThermal Models 1
High Speed Converter Toolbox for MATLAB
Open ToolEvaluation Kits
AD9081 Evaluation Board
Resources
ADS9-V2EBZ Evaluation Board