AD9691
RECOMMENDED FOR NEW DESIGNS14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter
- Part Models
- 2
- 1ku List Price
- Starting From $741.24
Part Details
- JESD204B (Subclass 1) coded serial digital outputs
- 1.9 W total power per channel (default settings)
- SFDR = 77 dBFS at 340 MHz
- SNR = 63.4 dBFS at 340 MHz (AIN = −1.0 dBFS)
- Noise density = −152.6 dBFS/Hz
- 1.25 V, 2.50 V, and 3.3 V dc supply operation
- No missing codes
- 1.58 V p-p differential full scale input voltage
- Flexible termination impedance
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential - 1.5 GHz usable analog input full power bandwidth
- 95 dB channel isolation/crosstalk
- Amplitude detection bits for efficient AGC implementation
- 2 integrated wideband digital processors per channel
12-bit NCO, up to 4 cascaded half-band filters - Integer clock divide by 1, 2, 4, or 8
- Flexible JESD204B lane configurations
- Timestamp feature
- Small signal dither
The AD9691 is a dual, 14-bit, 1.25 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. The device is designed for sampling wide bandwidth analog signals of up to 1.5 GHz.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO) and four half-band decimation filters.
In addition to the DDC blocks, the AD9691 has a programmable threshold detector that allows monitoring of the incoming signal power using the fast detect output bits of the ADC. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, four- or eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± input pins.
The AD9691 is available in a Pb-free, 88-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.
Product Highlights
- Low power consumption analog core, 14-bit, 1.25 GSPS dual analog-to-digital converter (ADC) with 1.9 W per channel.
- Wide full power bandwidth supports IF sampling of signals up to 1.5 GHz.
- Buffered inputs with programmable input termination eases filter design and implementation.
- Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.
- Programmable fast overrange detection.
- 12 mm × 12 mm 88-lead LFCSP.
Applications
- Communications (wideband receivers and digital predistortion)
- Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)
- DOCSIS 3.x CMTS upstream receive paths
- High speed data acquisition systems
Documentation
Data Sheet 1
FPGA Interoperability Reports 2
Analog Dialogue 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9691BCPZ-1250 | 88-Lead LFCSP (12mm x 12mm w/ EP) | ||
| AD9691BCPZRL7-1250 | 88-Lead LFCSP (12mm x 12mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Jun 26, 2023 - 23_0025 Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor |
||
| AD9691BCPZ-1250 | PRODUCTION | |
| AD9691BCPZRL7-1250 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Evaluation Software 1
JESD204x Frame Mapping Table Generator
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
Can't find the software or driver you need?
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 3 | ||
| LTC6955 | LAST TIME BUY | Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
| LTC6953 | LAST TIME BUY | Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support |
| HMC7043 | RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C |
| Clock Generation Devices 4 | ||
| LTC6951 | LAST TIME BUY | Ultralow Jitter Multi-Output Clock Synthesizer with Integrated VCO |
| LTC6952 | LAST TIME BUY | Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
| HMC7044 | RECOMMENDED FOR NEW DESIGNS | High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
| AD9528 | RECOMMENDED FOR NEW DESIGNS | JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs |
Tools & Simulations
ADC Companion Transport Layer RTL Code Generator Tool
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
Open ToolEvaluation Kits
AD9680/AD9234/AD9690 Evaluation Board