New Content (1)
Features and Benefits
- Flexible reconfigurable common platform design
- 4 DACs and 2 ADCs (4D2A) and 2D2A options
- Supports single, dual, and quad band
- Datapaths and DSP blocks are fully bypassable
- DAC to ADC sample rate ratios of 1, 2, 3, and 4
- On-chip PLL with multichip synchronization
- External RFCLK input option for off-chip PLL
- Maximum DAC sample rate up to 12 GSPS
- Maximum data rate up to 12 GSPS using JESD204C
- Useable analog bandwidth to 8 GHz
- Maximum ADC sample rate up to 6 GSPS
- Maximum data rate up to 6 GSPS using JESD204C
- Useable analog bandwidth to 8 GHz
- ADC ac performance at 6 GSPS, input at 2.7 GHz, −1 dBFS
- Full-scale input voltage: 1.475 V p-p
- Noise density: −147.5 dBFS/Hz
- Noise figure: 25.3 dB
- HD2: −72 dBFS
- HD3: −68 dBFS
- Worst other (excluding HD2 and HD3): −78 dBFS
- DAC ac performance at 12 GSPS, output at 2.6 GHz
- Full-scale output current range: 6.43 mA to 37.75 mA
- Two-tone IMD3 (−6 dBFS per tone): −72 dBc
- NSD, single-tone: −160 dBc/Hz
- SFDR, single-tone: 75 dBc
- Versatile digital features
- Selectable interpolation and decimation filters
- Configurable DDC and DUC
- 8 fine complex DUCs and 4 coarse complex DUCs
- 8 fine complex DDCs and 4 coarse complex DDCs
- 48-bit NCO per DUC or DDC
- Option to bypass fine and coarse DUC/DDC
- Programmable 192-tap PFIR filter for receive equalization
- Supports 4 different profile settings loaded via GPIO
- Programable delay per data path
- Receive AGC support
- Fast detect with low latency for fast AGC control
- Signal monitor for slow AGC control
- Dedicated AGC support pins
- Transmit DPD support
- Fine DUC channel gain control and delay adjust
- Coarse DDC delay adjust for DPD observation path
- Auxiliary features
- Fast frequency hopping
- Direct digital synthesis (DDS)
- Low latency loopback modes (receive datapath data can be routed to the transmit datapaths)
- ADC clock driver with selectable divide ratios
- Power amplifier downstream protection circuitry
- On-chip temperature monitoring unit
- Flexible GPIO pins
- TDD power savings option
- SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps
- 8 lanes JESD204B/C transmitter (JT×) and 8 lanes
- JESD204B/C receiver (JR×)
- JESD204B compliance with the maximum 15.5 Gbps
- JESD204C compliance with the maximum 24.75 Gbps
- Supports real or complex digital data (8-, 12-, 16-, or 24-bit)
- 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch
The AD9082 mixed signal front-end (MxFE®) is a highly integrated device with a 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) core, and 12-bit, 6 GSPS maximum sample rate, RF analog-to-digital converter (ADC) cores. The AD9082 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) having wide instantaneous bandwidth. The device features eight transmit lanes and eight receive lanes that support 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B standards. The device also has an on-chip clock multiplier and digital signal processing (DSP) capability targeted at either wideband or multiband, direct to RF applications. The DSP datapaths can be bypassed to allow a direct connection between the converter cores and the JESD204B/C data transceiver port. The device also features low latency loopback, frequency hopping modes, and datapath multiplexer (mux) configurations useful for phase array radar system and electronic warfare applications. Two models for the AD9082 are offered. The 4D2AC model supports four DACs and two ADCs. The 2D2AC model supports two DACs and two ADCs.
- Wireless communications infrastructure
- Microwave point-to-point, E-band and 5G mmWave
- Broadband communications systems
- DOCSIS 3.1 and 4.0 CMTS
- Phased array radar and electronic warfare
- Electronic test and measurement systems
Markets and Technologies
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (3)
The AD9082-FMCA-EBZ evaluation board includes all of the support circuitry required to operate the AD9082 in various modes and configurations. The application software used to interface with the device is also described. The AD9082-FMCA-EBZ evaluation board connects to the Analog Devices, Inc., ADS9-V2EBZ for evaluation with the ACE software. The boards can also interface to commercially available field- programmable gate array (FPGA) development boards from Xilinx® or Intel®. Information on how to use these platforms to evaluate the AD9081 or AD9082 is available in the Using the AD-FMC-SDCARD section.
The ACE software allows the user to set up the AD9081 or AD9082 in various modes, and capture analog-to-digital converter (ADC) data for analysis. The PGDownloaderLite software generates and transmits vectors to the DACs, which can then be sent to a spectrum analyzer for further analysis. For more details, see the AD9081 and AD9082 data sheets, which must be consulted in conjunction with this user guide when using the evaluation boards.
Features & Benefits
- Fully functional evaluation boards for the AD9082
- PC software for control with ACE software
- On-board clocking provided by the HMC7044 manages device and FPGA clocking
- Option to switch to external direct clocking
UG-1578: System Development User Guide for the AD9081 and AD9082 Direct RF Sampling Transceivers (Rev. A)7.93 M
UG-1829: Evaluating the AD9081, AD9082, AD9986, or AD9988 Mixed Signal, Front-End RF Transceiver (Rev. 0)1.42 M
Evaluating the AD9082/AD9081 Mixed Signal Front-end (MxFE™) and the AD9988/AD9986 Direct RF Sampling TransceiversWIKI
When connected to a specified Analog Devices high speed converter evaluation board, the ADS9-V2EBZ works as a data capture/transmit board. Designed to support the highest speed JESD204B/C data converters, the FPGA on the ADS9-V2EBZ acts as the data receiver for high speed ADC's, and as the transmitter for high speed DAC's.
Features & Benefits
Xilinx Kintex Ultrascale+ XCKU15P-2FFVE1517E FPGA.
- One (1) FMC+ connector.
- Twenty (20) 28Gbps transceivers supported by one (1) FMC+ connector.
- HMC DRAM
- Simple USB 3.0 port interface.
- Two micro SD cards are included, "TRX" -- for ADRV9026 evaluation boards and "HSX" -- for MxFE™ evaluation boards.
The Quad-MxFE System Development Platform contains four MxFE® software defined, direct RF sampling transceivers, as well as associated RF front-ends, clocking, and power circuitry. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a 16 transmit/16 receive channel direct sampling phased array at L/S/C band (0.1 GHz to ~5GHz). The Rx & Tx RF front-end has drop-in configurations that allow for customized frequency ranges, depending on the user’s application.
The Quad-MxFE System Development Platform highlights a complete system solution. It is intended as a testbed for demonstrating multi-chip synchronization as well as the implementation of system level calibrations, beamforming algorithms, and other signal processing algorithms. The system is designed to mate with a VCU118 Evaluation Board from Xilinx®, which features the Virtex® UltraScale+™ XCVU9P FPGA, with provided reference software, HDL code, and MATLAB system-level interfacing.
In addition to the Quad-MxFE Digitizing Card, the kit also contains a 16Tx / 16Rx Calibration Board that is used to develop system-level calibration algorithms, or otherwise more easily demonstrate power-up phase determinism in situations pertinent to their own use case. The Calibration Board also allows the user to demonstrate combined-channel dynamic range, spurious, and phase noise improvements and can also be controlled via a free MATLAB add-on when connected to the PMOD interface of the VCU118.
The system can be used to enable quick time-to-market development programs for applications like:
- ADEF (Phased-Array, RADAR, EW, SATCOM)
- Communications Infrastructure (Multiband 5G and mmWave 5G)
- Electronic Test and Measurement
Features & BenefitsQuad-MxFE Digitizing Card
- Multi-Channel, Wideband System Development Platform Using MxFE
- Mates With Xilinx VCU118 Evaluation Board (Not Included)
- 16x RF Receive (Rx) Channels (32x Digital Rx Channels)
- Total 16x 1.5GSPS to 4GSPS ADC
- 48x Digital Down Converters (DDCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
- 16x Programmable Finite Impulse Response Filters (pFIRs)
- 16x RF Transmit (Tx) Channels (32x Digital Tx Channels)
- Total 16x 3GSPS to 12GSPS DAC
- 48x Digital Up Converters (DUCs) , Each Including Complex Numerically-Controlled Oscillators (NCOs)
- Flexible Rx & Tx RF Front-Ends
- Rx: Filtering, Amplification, Digital Step Attenuation for Gain Control
- Tx: Filtering, Amplification
- On-Board Power Regulation from Single 12V Power Adapter (Included)
- Flexible Clock Distribution
- On-Board Clock Distribution from Single External 500MHz Reference
- Support for External Converter Clock per MxFE
- Mates to Quad-MxFE Digitizing Card & VCU118 PMOD Interface (Cable Included)
- Provides Both Individual Adjacent Channel Loopback and Combined Channel Loopback Options
- Combined Tx Channels Out Via SMA Option
- Combined Rx Channels In Via SMA Option
- On-Board Log Power Detectors With AD5592R Output To VCU118 Over PMOD
- On-Board Power Regulation from Single 12V Power Adapter (Included)
Easy Control Tools and Platform Interfaces to Simplify Software Framework Developments:
- IIO Oscilloscope GUI
- MATLAB Add-Ons & Example Scripts
- Example HDL Builds including JESD204b/JESD204c Bring-Up
- Embedded Software Solutions for Linux and Device Drivers
- MATLAB System Applications GUI
- Multi-Chip Synchronization for Power-Up Phase Determinism
- System-Level Amplitude/Phase Alignment Using NCOs
- Low-Latency ADC-to-DAC Loopback Bypassing JESD Interface
- pFIR Control for Broadband Channel-to-Channel Amplitude/Phase Alignment
- Fast-Frequency Hopping
- Calibration Board MATLAB Driver File
- FPGA Programming MATLAB Script
Documentation & Resources
RF, Microwave, and Millimeter Wave Product Selection Guide7/13/20189M
Intel AN-976 (AD9081/AD9082 Tx Path JESD204C Interoperability with Agilex)2/22/2023
Intel AN-960 (AD9081/AD9082 Rx Path JESD204C Interoperability with Agilex)2/22/2023
Intel AN-949 (AD9081/AD9082 Tx Path JESD204C Interoperability with Stratix 10)7/27/2021
Intel AN-927 (AD9081/AD9082 Rx Path JESD204C Interoperability with Stratix 10)10/14/2020
Intel AN-916 (AD9081/AD9082 JESD204C Interoperability with Stratix 10)6/22/2020
Space-based SATCOM Signal Chain9/13/2022
MxFE Evaluation Platform Demonstration Series8/1/2022SERIES
Analog Devices' Next Generation 5G mmW Radio from Bits-To-Beams6/3/2022
"QUAD MxFE" Calibration Board Introduction & Unboxing4/11/2022
16Tx/16Rx Phased Array Prototyping Platform "QUAD MxFE" Unboxing4/11/2022
Analog Devices MxFE® RF Data Converter Transceivers3/3/2022
Easy Digital Filter Applications for Not-So-Easy RF System Designs3/6/2023
High IF Sampling Puts Wideband Software-Defined Radio Within Reach5/6/2022 Analog Dialogue
Considering GSPS ADCs in RF Systems11/1/2021
Integrated Hardened DSP on DAC/ADC ICs Improves Wideband Multichannel Systems5/1/2021
How Error Vector Magnitude (EVM) Measurement Improves Your System-Level Performance4/1/2021
SFDR Considerations in Multi-Octave Wideband Digital Receivers1/8/2021 Analog Dialogue
Power-Up Phase Determinism Using Multichip Synchronization Features in Integrated Wideband DACs and ADCs10/1/2020
System-Level LO Phase Noise Model for Phased Arrays with Distributed Phase-Locked Loops11/1/2018
Software & Systems Requirements
API Device Drivers
Device Application Programming Interface (API) C code drivers provided as reference code that allows the user to quickly configure the product using high-level function calls. The library acts as an abstraction layer between the application and the hardware. The API is developed in C99 to ensure agnostic processor and operating system integration. Customers can port this application layer code to their embedded systems by integrating their platform-specific code base to the API HAL layer.
To request this software package, go to the Software Request Form signed in with your MyAnalog account and under “Target Hardware” select “High Speed Data Converters” and choose the desired API product package. You will receive an email notification once the software is provided to you.
Tools & Simulations
Software and Simulation
Keysight ADS workbook and s-parameter files for simulating the frequency response of the AD908x DAC, ADC, and CLK interfaces. See Application note AN-2065: Optimizing RF performance of the AD9081 and AD9082” for instructions on how to use the models.
The JESD204B/C Mode Selector Tool is a simple command line-based Windows executable that can be used to narrow down the number of JESD204x modes to only include those modes that support the user’s specific application use case. The tool guides the user through a use case description flow chart and gives the user a small list of applicable transmit and/or receive modes to choose from. This tool is applicable to the AD9081, AD9082, AD9177, AD9207, AD9209, AD9986, and AD9988.
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.
AD9082 Companion Parts
Recommended Power Products
DC-to-DC switching regulators:
- For a low noise linear regulators: ADP1765, ADP7158, ADM7172, ADM7150.
Recommended Clock Distribution Device
Recommended Clock Generation Device
Recommended RF Amplifiers
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
|Part Number||Material Declaration||Reliability Data||Pin/Package Drawing||CAD Symbols, Footprints & 3D Models|
|AD9082BBPZ-2D2AC||Material Declaration||Reliability Data||324-Ball BGA_ED (15mm x 15mm x 1.58mm)|
|AD9082BBPZ-4D2AC||Material Declaration||Reliability Data||324-Ball BGA_ED (15mm x 15mm x 1.58mm)|
|AD9082BBPZ4D2ACCSL||Material Declaration||Reliability Data||324-Ball BGA_ED (15mm x 15mm x 1.58mm)|
|AD9082BBPZRL-2D2AC||Material Declaration||Reliability Data||324-Ball BGA_ED (15mm x 15mm x 1.58mm)|
|AD9082BBPZRL-4D2AC||Material Declaration||Reliability Data||324-Ball BGA_ED (15mm x 15mm x 1.58mm)|
|Wafer Fabrication Data|
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.