Features and Benefits

  • Flexible reconfigurable common platform design
    • 4 DACs and 2 ADCs (4D2A)
    • Supports single, dual, and quad band
    • Maximum DAC/ADC sample rate up to 12 GSPS/6 GSPS
      • DAC to ADC sample rate ratios of 1, 2, 3, and 4
      • ADC and DAC datapath bypass option
      • Analog bandwidth to 8 GHz
      • Full-scale output current range, ac coupling: 7 mA to 40 mA
    • On-chip PLL with multichip synchronization
      • External RFCLK input option
  • ADC ac performance at 6 GSPS
    • Full-scale input voltage: 1.475 V p-p
    • Full-scale sine wave input power: 4.4 dBm
    • Noise density: −153 dBFS/Hz
    • Noise figure: 25.3 dB
    • HD2: −65.2 dBFS at 2.7 GHz
    • HD3: −70.8 dBFS at 2.7 GHz
    • Worst other (excluding HD2 and HD3): −68.5 dBFS at 2.7 GHz
  • DAC ac performance at 3.7 GHz output
    • 2-tone IMD3 (−7 dBFS per tone): −78.9 dBc
    • NSD, single-tone, fDAC = 12 GSPS: −155.1 dBc/Hz
    • SFDR, single-tone, fDAC = 12 GSPS: −70 dBc
  • Versatile digital features
    • Supports real or complex digital data (8-, 12-, 16-, or 24-bit)
    • Selectable interpolation and decimation filters
    • Configurable DDC and DUC
      • 8 fine complex DUCs and 4 coarse complex DUCs
      • 8 fine complex DDCs and 4 coarse complex DDCs
      • 48-bit NCO per DUC/DDC
      • Option to bypass fine and coarse DUC/DDC
  • Programmable 192-tap PFIR filter for receive equalization
    • Supports 4 different profile settings loaded via GPIO
  • Programable delay per data path
  • Receive AGC support
    • Fast detect with low latency for fast AGC control
    • Signal monitor for slow AGC control
    • Dedicated AGC support pins
  • Transmit DPD support
    • Fine DUC channel gain control and delay adjust
    • Coarse DDC delay adjust for DPD observation path
  • Auxiliary features
    • Fast frequency hopping
    • Direct digital synthesis (DDS)
    • Low latency digital loopback mode (ADC to DAC)
    • ADC clock driver with selectable divide ratios
    • Power amplifier downstream protection circuitry
    • On-chip temperature monitoring unit
    • Flexible GPIOx pins
    • TDD power savings option
  • SERDES JESD204B/JESD204C interface, 16 lanes up to 16.22 Gbps
    • 8 lanes per DACs and ADCs
    • JESD204B compatible with the maximum 15.5 Gbps lane rate
    • JESD204C compatible with the maximum 16.22 Gbps lane rate
    • Sample and bit repeat mode for lane rate matching
  • Total power consumption: 11.45 W typical
  • 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

Product Details

The mixed signal front-end (MxFE®) is a highly integrated device with a 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) core, and 12-bit, 6 GSPS rate, RF analog-to-digital converter (ADC) core. The AD9082 supports four transmitter channels and two receiver channels. The AD9082 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) having wide instantaneous bandwidth. The device features a 16 lane, 16.22 Gbps JESD204C or 15.5 Gbps JESD204B data transceiver port, an on-chip clock multiplier, and a digital signal processing (DSP) capability targeted at either wideband or multiband, direct to RF applications. The AD9082 also features a bypass mode that allows the full bandwidth capability of the ADC and/or DAC cores to bypass the DSP datapaths. The device also features low latency loopback and frequency hopping modes targeted at phase array radar system and electronic warfare applications.


  • Wireless communications infrastructure
  • Microwave point-to-point, E-band and 5G mmWave
  • Broadband communications systems
  • DOCSIS 3.1 and 4.0 CMTS
  • Phased array radar and electronic warfare
  • Electronic test and measurement systems

Product Lifecycle icon-recommended Recommended for New Designs

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

Evaluation Kits (4)

Software & Systems Requirements

Device Drivers

API Device Drivers

Device Application Programming Interface (API) C code drivers provided as reference code that allows the user to quickly configure the product using high-level function calls. The library acts as an abstraction layer between the application and the hardware. The API is developed in C99 to ensure agnostic processor and operating system integration. Customers can port this application layer code to their embedded systems by integrating their platform-specific code base to the API HAL layer.

To request this software package, go to the Software Request Form signed in with your MyAnalog account and under “Target Hardware” select “High Speed Data Converters” and choose the desired API product package. You will receive an email notification once the software is provided to you.

Tools & Simulations

Design Tools

Companion Transport Layer RTL Code Generator Tool (Rev. 1.0)

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

JESD204x Frame Mapping Table Generator

The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.

Product Recommendations

AD9082 Companion Parts

Recommended Clock Distribution Device

Recommended Clock Generation Device

Recommended RF Amplifiers

Recommended VGA's

Design Resources

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

PCN-PDN Information

Sample & Buy

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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

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Up to two boards can be purchased through Analog.com. To order more than two, please purchase through one of our listed distributors.
Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.