Features and Benefits
- Flexible reconfigurable radio common platform design
- Transmit/receive channel bandwidth up to 1.2 GHz/2.4 GHz (4T2R)
- RFDAC/RFADC RF frequency range up to 7.5 GHz
- On-chip PLL with multichip synchronization
- External RFCLK input option
- Versatile digital features
- Configurable digital up/down conversion (DDC and DUC)
- 8 fine complex DUCs and 4 coarse complex DUCs
- 8 fine complex DDCs and 4 coarse complex DDCs, 2 independent
- 48-bit NCO per DUC/DDC
- Programmable 192-tap PFIR filter for receive equalization
- Supports 4 different profile settings loaded via GPIO
- Receive AGC support
- Fast detect with low latency for fast AGC control
- Signal monitor for slow AGC control
- Dedicated AGC support pins
- Transmit DPD support
- Programmable delay and gain per transmit data path
- Coarse DDC delay adjust for DPD observation path
- Configurable digital up/down conversion (DDC and DUC)
- Auxiliary features
- Power amplifier downstream protection circuitry
- On-chip temperature monitoring unit
- Programmable GPIO pins supporting different user configurations
- ADC clock driver with selectable divide ratios
- TDD power savings option and sharing ADCs
- SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps
- 8 lanes per each DAC and ADC
- JESD204B compatible with maximum 15.5 Gbps lane rate
- JESD204C compatible with maximum 24.75 Gbps lane rate
- Supports real or complex digital data (8-bit, 12-bit, 16-bit, or 24-bit)
- 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch
The AD9986 is a highly integrated device with a 16-bit, 12 GSPS maximum sample rate RF DAC core, and a 12-bit, 6 GSPS rate RF ADC core. The AD9986 supports four transmitter channels and two receiver channels with four transmitter, two receiver (4T2R) configuration. The AD9986 is well suited for 2-antenna and 4-antenna transmitter applications requiring a wide bandwidth observation receiver path for the digital predistortion. The AD9986 supports up to a 6 GSPS complex transmit and receive data rate in single channel mode. The maximum radio channel bandwidth supported is 1.2 GHz and 2.4 GHz for the transmit and receive paths, respectively (4T2R). The AD9986 features a 16 lane, 24.75 Gbps JESD204C or 15.5 Gbps JESD204B serial data port, an on-chip clock multiplier, and digital signal processing capability targeted at multiband, direct-to-RF radio applications.
- Wireless communications infrastructure
- W-CDMA, LTE, LTE-A, Massive-MIMO
- Microwave point-to-point, E-band, and 5G mm Wave
- Broadband communications systems
- DOCSIS 3.1 and 4.0 CMTS
- Communications test and measurement system
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (2)
The user guide describes the AD9081-FMCA-EBZ, AD9082-FMCA-EBZ, AD9986-FMCB-EBZ, and AD9988-FMCB-EBZ evaluation boards, which provide all of the support circuitry required to operate the AD9081, AD9082, AD9986, AD9988, AD9207, AD9209, or AD9177 in their various modes and configurations. The application software used to interface with the devices is also described. These evaluation boards connect to the Analog Devices, Inc., ADS9-V2EBZ for evaluation with the ACE software.
These evaluation boards can also interface to commercially available field-programmable gate array (FPGA) development boards from Xilinx® or Intel®. Information on how to use these platforms to evaluate the AD9081 or the AD9082 is available in the Using the AD-FMC-SDCARD section.
The ACE software allows the user to set up the MxFE® in various modes and to capture analog-to-digital converter(ADC) data for analysis. The DPGDownloaderLite software (included in ACE installation) generates and transmits vectors to the digital-to-analog converters (DACs), which can then be sent to a spectrum analyzer for further analysis.
For additional information, see the AD9081, AD9082, AD9986, AD9988, AD9207, AD9209, or AD9177 data sheets and the UG-1578, the device user guide, which must be consulted in conjunction with the user guide when using the evaluation boards.
When connected to a specified Analog Devices high speed converter evaluation board, the ADS9-V2EBZ works as a data capture/transmit board. Designed to support the highest speed JESD204B/C data converters, the FPGA on the ADS9-V2EBZ acts as the data receiver for high speed ADC's, and as the transmitter for high speed DAC's.
Features & Benefits
Xilinx Kintex Ultrascale+ XCKU15P-2FFVE1517E FPGA.
- One (1) FMC+ connector.
- Twenty (20) 28Gbps transceivers supported by one (1) FMC+ connector.
- HMC DRAM
- Simple USB 3.0 port interface.
- Two micro SD cards are included, "TRX" -- for ADRV9026 evaluation boards and "HSX" -- for MxFE™ evaluation boards.
Documentation & Resources
Intel AN-976 (AD9081/AD9082 Tx Path JESD204C Interoperability with Agilex)2/22/2023
Intel AN-960 (AD9081/AD9082 Rx Path JESD204C Interoperability with Agilex)2/22/2023
Intel AN-949 (AD9081/AD9082 Tx Path JESD204C Interoperability with Stratix 10)7/27/2021
Intel AN-927 (AD9081/AD9082 Rx Path JESD204C Interoperability with Stratix 10)10/14/2020
Intel AN-916 (AD9081/AD9082 JESD204C Interoperability with Stratix 10)6/22/2020
Software & Systems Requirements
API Device Drivers
Device Application Programming Interface (API) C code drivers provided as reference code that allows the user to quickly configure the product using high-level function calls. The library acts as an abstraction layer between the application and the hardware. The API is developed in C99 to ensure agnostic processor and operating system integration. Customers can port this application layer code to their embedded systems by integrating their platform-specific code base to the API HAL layer.
To request this software package, go to the Software Request Form signed in with your MyAnalog account and under “Target Hardware” select “High Speed Data Converters” and choose the desired API product package. You will receive an email notification once the software is provided to you.
Tools & Simulations
Software and Simulation
Keysight ADS workbook and s-parameter files for simulating the frequency response of the AD908x DAC, ADC, and CLK interfaces. See Application note AN-2065: Optimizing RF performance of the AD9081 and AD9082” for instructions on how to use the models.
These command line executable tool generates a Verilog module which implements the JESD204 transmitter transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
The JESD204B/C Mode Selector Tool is a simple command line-based Windows executable that can be used to narrow down the number of JESD204x modes to only include those modes that support the user’s specific application use case. The tool guides the user through a use case description flow chart and gives the user a small list of applicable transmit and/or receive modes to choose from. This tool is applicable to the AD9081, AD9082, AD9177, AD9207, AD9209, AD9986, and AD9988.
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.
AD9986 Companion Parts
Recommended Power Products
DC-to-DC switching regulators:
- For a low noise linear regulators: ADP1765, ADP7158, ADM7172, ADM7150.
Recommended Clock Distribution Device
Recommended Clock Generation Device
Recommended RF Amplifiers
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
|Part Number||Material Declaration||Reliability Data||Pin/Package Drawing||CAD Symbols, Footprints & 3D Models|
|AD9986BBPZ-4D2AC||Material Declaration||Reliability Data||324-Ball BGA_ED (15mm x 15mm x 1.58mm)|
|AD9986BBPZRL-4D2AC||Material Declaration||Reliability Data||324-Ball BGA_ED (15mm x 15mm x 1.58mm)|
|Wafer Fabrication Data|
Sample & Buy
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