Features and Benefits

  • Output frequency range: 800 MHz to 12.8 GHz
  • Jitter = 18 fsRMS (Integration BW: 100 Hz to 100 MHz)
  • Jitter = 27 fsRMS (ADC SNR Method)
  • Wideband Noise Floor: -160 dBc/Hz @12 GHz
  • PLL Specifications:
    • -239 dBc/Hz: Normalized In-Band Phase Noise Floor
    • -147 dBc/Hz: Normalized In-Band 1/f Noise
    • Phase Detector Frequency up to 500 MHz
    • Reference Input Frequency up to 1 GHz
    • Typical -100 dBc PFD spurs
  • Reference to Output Delay Specifications:
    • Part-to-Part Standard Deviation: 3 ps
    • Temperature Drift: 0.03 ps/℃
    • Adjustment Step Size: <+/-0.1 ps
  • Multi-chip Output Phase Alignment
  • 3.3 V and 5 V Power supplies
  • 7 mm x 7 mm 48 Lead LGA

Product Details

The ADF4377 is a high performance, ultralow jitter, dual output integer-N phased locked loop (PLL) with integrated voltage controlled oscillator (VCO) ideally suited for data converter and mixed signal front end (MxFE) clock applications. The high performance PLL has a figure of merit of -239 dBc/Hz, ultralow 1/f Noise and a high phase frequency detector (PFD) frequency that can achieve ultralow in-band noise and integrated jitter. The ADF4377’s fundamental VCO and output divider generate frequencies from 800 MHz to 12.8 GHz. The ADF4377 integrates all necessary power supply bypass capacitors, saving board space on compact boards.

For multiple data converter and MxFE clock applications, the ADF4377 simplifies clock alignment and calibration routines required with other clock solutions, by implementing:

  • automatic reference to output synchronization,
  • extremely well match reference to output delays across process, voltage, and temperature, and
  • sub-ps, jitter free reference to output delay adjustment capability.
  • These features allow for predictable and precise multi-chip clock and SYSREF alignment. JESD204B and JESD204C subclass 1 solutions are supported by pairing the ADF4377 with an integrated circuit(IC) that distributes pairs of reference and SYSREF signals.


  • High Performance Data Converter and MxFE Clocking
  • Wireless infrastructure (MC-GSM, 5G)
  • Test and Measurement
  • For more information please contact ADI at ADF_NewProducts@analog.com

    Product Lifecycle icon-recommended Pre-Release

    This product is new and engineering validation may still be underway. Quantities may be limited and design specifications may change while we ready the product for release to production.

    Tools & Simulations

    IBIS Models

    Design Tools


    ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.

    Product Recommendations

    ADF4377 Companion Parts

    Recommended Recommended Ultra Low Noise/High PSRR LDO

    Recommended Reference & SYSREF Distribution

    Recommended Reference Distribution Buffer

    Design Resources

    ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

    Sample & Buy

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