AD9174
Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
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Overview
Features and Benefits
- Supports multiband wireless applications
- 3 bypassable, complex data input channels per RF DAC
- 3.08 GSPS maximum complex input data rate per input channel
- 1 independent NCO per input channel
- Proprietary, low spurious and distortion design
- 2-tone IMD3 = −83 dBc at 1.84 GHz, −7 dBFS/tone RF output
- SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output
- Flexible 8-lane, 15.4 Gbps JESD204B interface
- Supports single-band and multiband use cases
- Supports 12-bit high density mode for increased data throughput
- Multiple chip synchronization
- Supports JESD204B Subclass 1
- Selectable interpolation filter for a complete set of input data rates
- 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation
- 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation
- Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz
- Transmit enable function allows extra power saving and downstream circuitry protection
- High performance, low noise PLL clock multiplier
- Supports 12.6 GSPS DAC update rate
- Observation ADC clock driver with selectable divide ratios
- Low power
- 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch
Product Details
The AD9174 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates up to 12.6 GSPS. The device features an 8-lane, 15.4 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency (RF) wireless applications.
The AD9174 features three complex data input channels per RF DAC datapath. Each input channel is fully bypassable. Each data input channel (or channelizer) includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, multiband frequency planning. The AD9174 supports an input data rate of up to a 3.08 GSPS complex (inphase/quadrature (I/Q)), or up to 6.16 GSPS non-complex (real), and is capable of allocating multiple complex input data streams to the assigned channels for individual processing. Each group of three channelizers is summed into a respective main datapath for additional processing when needed. Each main datapath includes an interpolation filter and one 48-bit main NCO ahead of the RF DAC core. Using the modulator switch, the outputs of a main datapath can be either routed to DAC0 alone for operating as a single DAC, or routed to both DAC0 and DAC1 for operating as a dual, intermediate frequency DAC (IF DAC).
The AD9174 also supports ultrawide data rate modes that allow bypassing the channelizers and main datapaths to provide maximum data rates of up to 6.16 GSPS as a single, 16-bit DAC, up to 3.08 GSPS as a dual, 16-bit DAC, or up to 4.1 GSPS as a dual, 12-bit DAC.
Additionally, the main NCO blocks in the AD9174 contain a bank of 31, 32-bit NCOs, each with an independent phase accumulator. Combined with a 80 MHz serial peripheral interface (SPI) for programming the NCOs, this bank allows a phase coherent, fast frequency hopping (FFH) for applications where the NCO frequencies are continuously adjusted during operation.
The AD9174 is available in a 144-ball BGA_ED package.
Applications
- Wireless communications infrastructure
- Multiband base station radios
- Microwave/E-band backhaul systems
- Instrumentation, automatic test equipment (ATE)
- Radars and jammers
Product Highlights
- A low power, multichannel, dual DAC design reduces power consumption in higher bandwidth and multichannel applications, while maintaining performance.
- Supports single-band and multiband wireless applications with three bypassable complex data channels per RF DAC, or configurations that use the two main datapaths as two wideband complex data channels when using the built in modulator switch.
- A maximum complex data rate (per I or Q) of up to 3.08 GSPS with 16-bit resolution, and up to 4.1 GSPS with 12-bit resolution. The AD9174 can be alternatively configured as a dual DAC, with each DAC operating across an independent JESD204B link, at the previously described data rates.
- Ultrawide bandwidth single-DAC modes, supporting up to 6.16 GSPS data rates with 16-bit resolution.
Product Categories
Markets and Technologies
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
Documentation & Resources
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AD917x API Specification (Rev. 1.1)7/18/2017
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AD917x Evaluation Board User Guide7/12/2017WIKI
Tools & Simulations
IBIS Models
IBS
AD9174 IBIS Model
147.58 K
S-Parameters
ZIP
AD9174 S-Parameters
115.66 K
Design Tools
DAC Companion Transport Layer RTL Code Generator (Rev. 1.0)
These command line executable tool generates a Verilog module which implements the JESD204 transmitter transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
ADIsimPLL™
ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.
Product Recommendations
AD9174 Companion Parts
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
| Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
|---|---|---|---|---|
| AD9174BBPZ | Material Declaration | Reliability Data | 144 ball (10x10x1.71 w/6.6 mm EP) | |
| AD9174BBPZRL | Material Declaration | Reliability Data | 144 ball (10x10x1.71 w/6.6 mm EP) | |
| Wafer Fabrication Data |
Support & Discussions
AD9174 Discussions
RE: How to read or write the registers of AD9174 through SPI(p3)?
14 week(s) ago in Speed DACs
Sample & Buy
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Evaluation Boards
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.