New Content (1)
Features and Benefits
- 1.0 V and 1.8 V supply operation
- 125 MHz usable analog input bandwidth
- Sample rate up to 2 GSPS
- Noise spectral density in 100 MHz bandwidth = −145 dBFS/Hz, 2.0 GSPS encode
- SNR = 66 dBFS in 100 MHz bandwidth, 2.0 GSPS encode
- SNR = 82 dBFS in 15.625 MHz bandwidth, 2.0 GSPS encode
- SFDR = 60 dBc in 100 MHz bandwidth, 2.0 GSPS encode
- SFDR = 80 dBc in 15.625 MHz bandwidth, 2.0 GSPS encode
- Large signal dither
- 90 mW total power per channel at 2.0 GSPS (default settings), 35 mW power per channel (min)
- Flexible input range: 0.5 V p-p to 2 V p-p differential
- 90 dB channel crosstalk, 2.0 GSPS encode
- Digital processor
- CIC decimation filter
- Programmable DDC
- Data gating
- JESD204B subclass 1 encoded outputs
- Supports up to 16Gbps/lane
- Flexible sample data processing
- Flexible JESD204B lane configurations
- Serial port control
The AD9083 is a 16-channel, 125 MHz bandwidth, continuous time Σ-Δ (CTSD) ADC. The device features an on-chip, programmable, single-pole antialiasing filter and termination resistor that is designed for low power, small size, and ease of use.
The 16 ADC cores features a first-order, CTSD modulator architecture with integrated, background nonlinearity correction logic and self cancelling dither. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
The analog input and clock signals are differential inputs. Each ADC has a signal processing tile to filter out of band shaped noise from the Σ-Δ ADC and reduce the sample rate. Each tile contains a cascaded integrator comb (CIC) filter, a quadrature digital downconverter (DDC) with multiple finite input response (FIR) decimation filters (decimate by J block), or up to three quadrature DDC channels with averaging decimation filters for data gating applications.
Users can configure the Subclass 1 JESD204B based, high speed serialized output in a variety of lane configurations (up to four), depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, TRIG±, and SYNCINB± input pins.
The AD9083 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V capable 3-wire serial port interface (SPI).
The AD9083 is available in a Pb-free, 100-ball CSP_BGA and is specified over the −40°C to +85°C industrial temperature range.
This product is protected by a US patent.
- Millimeter wave imaging
- Electronic beam forming and phased arrays
- Multichannel wideband receivers
- Electronic support measures
- Continuous time, Σ-Δ analog-to-digital converters (ADCs) support signal bandwidths of up to 125 MHz with low power and minimal filtering.
- Integrated digital processing blocks reduce data payload and lower overall system cost.
- Configurable JESD204B interface reduces printed circuit board (PCB) complexity.
- Flexible power-down options.
- SPI interface controls various product features and functions to meet specific system requirements.
- Small, 9 mm × 9 mm, 100-ball CSP_BGA package, simple interface, and integrated digital processing save PCB space.
Markets and Technologies
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (2)
The AD9083EBZ evaluation board includes all of the support circuitry required to operate the AD9083 in various modes and configurations. The application software used to interface with the device is also described. The AD9083EBZ evaluation board connects to the Analog Devices, Inc., ADS8-V3EBZ for evaluation with the ACE software.
The ACE software allows the user to set up the AD9083 in various modes, and capture analog-to-digital converter (ADC) data for analysis.
Features & Benefits
- Fully functional evaluation board for the AD9083
- PC software for control with ACE software
- On-board clocking provided by the AD9528 manages device and FPGA clocking
- Option to switch to external direct clocking
When connected to a specified Analog Devices high speed converter evaluation board, the ADS8-V3EBZ works with ADI evaluation software as a data capture/transmit and control interface. Designed to support high speed data converters with JESD204B/C serial line rates up to 16.375 Gbps, the FPGA on the ADS8-V3EBZ acts as the data receiver for high speed ADC's, and as the transmitter for high speed DAC's.
Limited to use cases where lane rates are less than 16.375 Gbps due to the FPGA capability. (Applies to AD9081 and AD9082.)
Features & Benefits
- Xilinx Kintex UltraScale XCKU040-3FFVA1156E FPGA
- Twenty (20) 16.375 Gbps transceivers supported by one (1) FMC+ connector
- Dual-bank DDR4 SDRAM
- Simple USB 3.0 serial port interface
- One (1) micro SD card is included for high speed converter evaluation board support
Software & Systems Requirements
API Device Drivers
Device Application Programming Interface (API) C code drivers provided as reference code that allows the user to quickly configure the product using high-level function calls. The library acts as an abstraction layer between the application and the hardware. The API is developed in C99 to ensure agnostic processor and operating system integration. Customers can port this application layer code to their embedded systems by integrating their platform-specific code base to the API HAL layer.
To request this software package, go to the Software Request Form signed in with your MyAnalog account and under “Target Hardware” select “High Speed Data Converters” and choose the desired API product package. You will receive an email notification once the software is provided to you.
Tools & Simulations
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Support & Discussions
Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.