Features and Benefits
- DC-coupled, 50 Ω matched output
- Up to 4.3 dBm output power, −9.5 dBm at 9 GHz
- DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2× NRZ mode
- Wide analog bandwidth
- DC to 9.0 GHz in 2× NRZ mode (12.0 GSPS DAC update rate)
- 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate)
- DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate)
- Power dissipation of 4.88 W in 2× NRZ mode (10 GSPS DAC update rate)
- Bypassable datapath interpolation
- 2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
- Instantaneous (complex) signal bandwidth
- 2.25 GHz with device clock at 5 GHz (2× interpolation)
- 1.8 GHz with device clock at 6 GHz (3× interpolation)
- Fast frequency hopping
- Integrated biCMOS buffer amplifier
The AD91661 is a high performance, wideband, on-chip vector signal generator composed of a high speed JESD204B serializer/deserializer (SERDES) interface, a flexible 16-bit digital datapath, a inphase/quadrature (I/Q) digital-to-analog converter (DAC) core, and an integrated differential to single-ended output buffer amplifier, matched to a 50 Ω load up to 10 GHz.
The DAC core is based on a quad-switch architecture, which is configurable to increase the effective DAC core update rate of up to 12.8 GSPS from a 6.4 GHz DAC sampling clock, with an analog output bandwidth of true dc to 9.0 GHz, typically. The digital datapath includes multiple interpolation filter stages, a direct digital synthesizer (DDS) block with multiple numerically controlled oscillators (NCOs) supporting fast frequency hopping (FFH), and additional FIR85 and inverse sinc filter stages to allow flexible spectrum planning.
The differential to single-ended buffer eliminates the need for a wideband balun, and supports the full analog output bandwidth of the DAC core. DC coupling the output allows baseband waveform generation without the need for external bias tees or similar circuitry, which makes the AD9166 uniquely suited for the most demanding high speed ultrawideband RF transmit applications.
The various filter stages enable the AD9166 to be configured for lower data rates, while maintaining higher DAC clock rates to ease the filtering requirements and reduce the overall system size, weight, and power.
The data interface receiver consists of up to eight JESD204B SERDES lanes, each capable of carrying up to 12.5 Gbps. To enable maximum flexibility, the receiver is fully configurable according to the data rate, number of SERDES lanes, and lane mapping required by the JESD204B transmitter.
In 2× nonreturn-to-zero (NRZ) mode of operation (with FIR85 enabled), the AD9166 can reconstruct RF carriers from true dc to the edge of the third Nyquist zone, or an analog bandwidth of true dc up to 9 GHz.
In mix mode, the AD9166 can reconstruct RF carriers in the second and third Nyquist zones while consuming lower power and maintaining a performance comparable to 2× NRZ mode.
In baseband modes, such as return-to-zero (RZ) and 1× NRZ, the AD9166 is ideal to reconstruct RF carriers from true dc to the edge of the first Nyquist zone while consuming lower power compared to 2× NRZ mode.
The quadrature DDS block can be configured as a digital upconverter to upconvert I/Q data samples to the desired location across the spectrum, in all three Nyquist zones.
The DDS also consists of a bank of 32 numerically controlled oscillators (NCOs), each with its own 32-bit phase accumulator. When combined with a 100 MHz serial peripheral interface (SPI), the DDS allows a phase coherent FFH, with a phase settling time as low as 300 ns.
The AD9166 is configured using a common SPI interface that monitors the status of all registers. The AD9166 is offered in a 324-ball, 15 mm × 15 mm, 0.8 mm pitch BGA_ED package.
- High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 9 GHz.
- Fully supports zero IF and other dc-coupled applications.
- Up to an eight-lane JESD204B SERDES interface, with various features to allow flexibility when interfacing to a JESD204B transmitter.
- Instrumentation: automated test equipment, electronic test and measurement, arbitrary waveform generators
- Electronic warfare: radars, jammers
- Broadband communications systems
- Local oscillator drivers
1 Protected by U.S. Patents 6,842,132 and 7,796,971.
Markets and Technologies
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (2)
The evaluation board connects to an ADS7-V2EBZ pattern generator for quick evaluation of the AD9166, a high speed, vector signal generator. The ADS7-V2EBZ automatically formats the signal data and sends it to the evaluation board across a JESD204B link, which simplifies evaluation of the device. The evaluation board is powered by the field-programmable gate array (FPGA) mezzanine card (FMC) power supply provided through the ADS7-V2EBZ. The board can also interface to commercially available field- programmable gate array (FPGA) development boards from Xilinx® or Intel®.
The evaluation board includes a clock buffer, the HMC7044, which provides a reference clock to the ADS7-V2EBZ and SYSREF± signals to both the ADS7-V2EBZ and the digital-to-analog converter (DAC) integrated inside the AD9166. The on-board ADF4372 generates a sampling clock for the DAC.
The reference and sampling clocks can be connected externally through the on-board Subminiature Version A (SMA) ports. SYSREF± can be connected from an external source, such as an FPGA development kit, across the FMC connector to the AD9166.
The various clock configurations are outlined in Figure 3 of the user guide. The clock paths can be selected by soldering 0 Ω resistors (jumpers) in the correct locations on the evaluation board and configuring the ADF4372 and HMC7044 as described in the On-Board Clocking section of the user guide.
Complete specifications for the AD9166 can be found in the AD9166 data sheet available from Analog Devices, Inc., and must be consulted in conjunction with the user guide when using the evaluation board.
The ADS7-V2 Evaluation Board was developed to support the evaluation of Analog Devices high speed A/D converters, D/A converters and Transceivers with JESD204B bit rates up to 13.1 Gbps. The Quick Start Wiki site listed below provides a high level overview of the platform. In addition, each use case of the board has its own section (e.g. Using the ADS7-V2 for High Speed A/D Converter Evaluation). The ADS7-V2 is intended to be used only with specified Analog Devices Evaluation Boards. The ADS7-V2 is not intended to be used as a development platform, and no support is available for standalone operation. Please refer to Xilinx and its approved distributors for FPGA Development Kits
Software & Systems Requirements
API Device Drivers
Device Application Programming Interface (API) C code drivers provided as reference code that allows the user to quickly configure the product using high-level function calls. The library acts as an abstraction layer between the application and the hardware. The API is developed in C99 to ensure agnostic processor and operating system integration. Customers can port this application layer code to their embedded systems by integrating their platform-specific code base to the API HAL layer.
To request this software package, go to the Software Request Form signed in with your MyAnalog account and under “Target Hardware” select “High Speed Data Converters” and choose the desired API product package. You will receive an email notification once the software is provided to you.
Tools & Simulations
Product Selection Guide (1)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
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