AD9643
14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
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Features
- SNR = 70.6 dBFS at 185 MHz AIN and 250 MSPS
- SFDR = 85 dBc at 185 MHz AIN and 250 MSPS
- −151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS
- Total power consumption: 785 mW at 250 MSPS
- 1.8 V supply voltages
- LVDS (ANSI-644 levels) outputs
- Integer 1-to-8 input clock divider (625 MHz maximum input)
- Sample rates of up to 250 MSPS
- IF sampling frequencies of up to 400 MHz
- Internal ADC voltage reference
- Flexible analog input range
- 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
- ADC clock duty cycle stabilizer
- 95 dB channel isolation/crosstalk
- Serial port control
- Energy saving power-down modes
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The AD9643 is a dual, 14-bit analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9643 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
The ADC output data is routed directly to the external, 14-bit, LVDS output port and formatted as either interleaved or channel multiplexed.
Flexible power-down options allow significant power savings, when desired.
Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.
The AD9643 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.
Product Highlights
- Integrated dual, 14-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.
- Operation from a single 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs.
- Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz.
- SYNC input allows synchronization of multiple devices.
- 3-pin, 1.8 V SPI port for register programming and register readback.
- Pin compatibility with the AD9613, allowing a simple migration down from 14 bits to 12 bits. This part is also pin compatible with the AD6649 and the AD6643.
Applications
- Communications
- Diversity radio systems
- Multimode digital receivers (3G)
- TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE
- I/Q demodulation systems
- Smart antenna systems
- General-purpose software radios
- Ultrasound equipment
- Broadband data applications
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Analog Devices Support Portal is a one-stop shop to answer all your ADI questions.
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AD9643
Documentation
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Application Note 17
AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev.0)
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev.0)
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev.0)
AN-807: Multicarrier WCDMA Feasibility (Rev.0)
AN-808: Multicarrier CDMA2000 Feasibility (Rev.0)
AN-345: Grounding for Low-and-High-Frequency Circuits
AN-282: Fundamentals of Sampled Data Systems
AN-878: High Speed ADC SPI Control Software (Rev.A)
AN-877: Interfacing to High Speed ADCs via SPI (Rev.B)
AN-737: How ADIsimADC Models an ADC (Rev.B)
AN-586: LVDS Outputs for High Speed A/D Converters (Rev.0)
AN-741: Little Known Characteristics of Phase Noise (Rev.0)
AN-501: Aperture Uncertainty and ADC System Performance (Rev.A)
AN-935: Designing an ADC Transformer-Coupled Front End
AN-835: Understanding High Speed ADC Testing and Evaluation
AN-1142: Techniques for High Speed ADC PCB Layout
AN-905: VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual
Technical Articles 2
Evaluation Design File 3
Tutorial 5
Technical Book 1
Device Drivers 1
Circuit Note 1
Webcast 2
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9643BCPZ-170 |
64-Lead LFCSP (9mm x 9mm w/ EP)
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| AD9643BCPZ-210 |
64-Lead LFCSP (9mm x 9mm w/ EP)
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| AD9643BCPZ-250 |
64-Lead LFCSP (9mm x 9mm w/ EP)
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| AD9643BCPZRL7-170 |
64-Lead LFCSP (9mm x 9mm w/ EP)
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| AD9643BCPZRL7-210 |
64-Lead LFCSP (9mm x 9mm w/ EP)
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| AD9643BCPZRL7-250 |
64-Lead LFCSP (9mm x 9mm w/ EP)
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- AD9643BCPZ-170
- Pin/Package Drawing
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64-Lead LFCSP (9mm x 9mm w/ EP)
- Documentation
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HTML
Material Declaration
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HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
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Ultra Librarian
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SamacSys
- AD9643BCPZ-210
- Pin/Package Drawing
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64-Lead LFCSP (9mm x 9mm w/ EP)
- Documentation
-
HTML
Material Declaration
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HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9643BCPZ-250
- Pin/Package Drawing
-
64-Lead LFCSP (9mm x 9mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9643BCPZRL7-170
- Pin/Package Drawing
-
64-Lead LFCSP (9mm x 9mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9643BCPZRL7-210
- Pin/Package Drawing
-
64-Lead LFCSP (9mm x 9mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9643BCPZRL7-250
- Pin/Package Drawing
-
64-Lead LFCSP (9mm x 9mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
Filter by Model
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Product Lifecycle
PCN
Jun 26, 2023
- 23_0025
Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor
AD9643BCPZ-170
PRODUCTION
AD9643BCPZ-210
PRODUCTION
AD9643BCPZ-250
PRODUCTION
AD9643BCPZRL7-170
PRODUCTION
AD9643BCPZRL7-210
PRODUCTION
AD9643BCPZRL7-250
PRODUCTION
Jul 27, 2020
- 20_0126
Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea
AD9643BCPZ-170
PRODUCTION
AD9643BCPZ-210
PRODUCTION
AD9643BCPZ-250
PRODUCTION
AD9643BCPZRL7-170
PRODUCTION
AD9643BCPZRL7-210
PRODUCTION
AD9643BCPZRL7-250
PRODUCTION
Filter by Model
Part Models
Product Lifecycle
PCN
Jun 26, 2023
- 23_0025
Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor
AD9643BCPZ-170
PRODUCTION
AD9643BCPZ-210
PRODUCTION
AD9643BCPZ-250
PRODUCTION
AD9643BCPZRL7-170
PRODUCTION
AD9643BCPZRL7-210
PRODUCTION
AD9643BCPZRL7-250
PRODUCTION
Jul 27, 2020
- 20_0126
Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea
AD9643BCPZ-170
PRODUCTION
AD9643BCPZ-210
PRODUCTION
AD9643BCPZ-250
PRODUCTION
AD9643BCPZRL7-170
PRODUCTION
AD9643BCPZRL7-210
PRODUCTION
AD9643BCPZRL7-250
PRODUCTION
Software & Part Ecosystem
Device Drivers
Looking for Evaluation Software? You can find it here
| Parts | Product Life Cycle | Description | ||
|---|---|---|---|---|
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Clock Distribution Devices3 |
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RECOMMENDED FOR NEW DESIGNS |
800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
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Clock Generation Devices6 |
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NOT RECOMMENDED FOR NEW DESIGNS |
14-Output, Low Jitter Clock generator |
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RECOMMENDED FOR NEW DESIGNS |
Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs |
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NOT RECOMMENDED FOR NEW DESIGNS |
6 Output, Dual Loop Clock Generator |
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RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
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Digital Control VGAs2 |
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Obsolete |
Wide Dynamic Range, High Speed, Digitally Controlled VGA |
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RECOMMENDED FOR NEW DESIGNS |
Ultralow Distortion IF Dual VGA |
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Fully Differential Amplifiers1 |
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RECOMMENDED FOR NEW DESIGNS |
3.3 GHz Ultralow Distortion RF/IF Differential Amplifier |
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Single-Ended to Differential Amplifiers2 |
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RECOMMENDED FOR NEW DESIGNS |
Ultralow Distortion Current Feedback Differential ADC Driver |
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RECOMMENDED FOR NEW DESIGNS |
Ultralow Distortion Differential ADC Driver (Dual) |
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Can't find the software or driver you need?
Request a Driver/SoftwareEvaluation Kits 2
HSC-ADC-EVALCZ
FPGA-Based Data Capture Kit
Features and Benefits
- 64kB FIFO Depth
- Works with single and multi-channel ADCs
- Use with VisualAnalog® software
- Based on Virtex-4 FPGA
- May require adaptor to interface with some ADC eval boards
- Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
- DDR Encode Rates on each channel
Product Detail
Resources
Software
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29.79 M
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EVAL-AD9643
AD9643 Evaluation Board
Product Detail
The AD9643-250EBZ is an evaluation board for the AD9643, dual 14-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations, It is designed to interface directly with the HSC-ADC-EVALCZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9643.
The AD9643 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeed.converters@analog.com.
Resources
Tools & Simulations 6
Virtual Eval - BETA
S-Parameter 1
S-Parameter
IBIS Model 1
Visual Analog
ADIsimRF
MathWorks® 1
Reference Designs 1
CN0242
High Performance, High IF, 75 MHz Bandwidth, 14-Bit, 250 MSPS Receiver Front End with Band-Pass Antialiasing Filter
Circuits from the lab
Info:Circuits from the lab
