AD6643

RECOMMENDED FOR NEW DESIGNS

AD6643

Dual IF Receiver

RECOMMENDED FOR NEW DESIGNS

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1ku List Price Starting From $82.07

Features

11-bit, 250 MSPS output data rate per channel
Performance with NSR enabled
- SNR: 74.5 dBFS in a 55 MHz band to 90 MHz at 250 MSPS
- SNR: 72.0 dBFS in a 82 MHz band to 90 MHz at 250 MSPS
Performance with NSR disabled
- SNR: 66.2 dBFS up to 90 MHz at 250 MSPS
- SFDR: 85 dBc up to 185 MHz at 250 MSPS
Total power consumption: 706 mW at 200 MSPS
1.8 V supply voltages

LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Internal ADC voltage reference
Flexible analog input range
- 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
Differential analog inputs with 400 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes

Additional Details

The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.

The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6643 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution.

The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6643 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.

When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6643 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6643 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required.

After digital signal processing, multiplexed output data is routed into an 11-bit output port such that the maximum data rate is 400 Mbps (DDR). These outputs are LVDS and support ANSI-644 levels.

The AD6643 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces compo-nent cost and complexity compared with traditional analog techniques or less integrated digital methods.

Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board level system testing.

The AD6643 is available in a Pb-free, RoHS-compliant, 64-lead, 9 mm × 9 mm lead frame chip scale package (LFCSP_VQ) and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

Product Highlights

Two ADCs are contained in a small, space-saving, 9 mm × 9 mm × 0.85 mm, 64-lead LFCSP package.
Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS.
LVDS digital output interface configured for low cost FPGA families.
Operation from a single 1.8 V supply.
Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode.
On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.

Applications

Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
- WCDMA, LTE, CDMA2000
- WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios

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Ask a Question

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Support

Analog Devices Support Portal is a one-stop shop to answer all your ADI questions.

Visit the ADI Support Page

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FAQs

Sales & Ordering FAQs

Part Models 4

1ku List Price Starting From $82.07

Technical Documents 21

AD6643: Dual IF Receiver Data Sheet (Rev.D) 04/21/2011

UG-293: Evaluating the AD9643/AD9613/AD6649/AD6643 Analog-to-Digital Converters 11/10/2011

AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev.0) 07/26/2006

AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev.0) 02/14/2015

AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev.0) 02/14/2015

AN-807: Multicarrier WCDMA Feasibility (Rev.0) 11/09/2007

AN-808: Multicarrier CDMA2000 Feasibility (Rev.0) 11/09/2007

AN-878: High Speed ADC SPI Control Software (Rev.A) 03/20/2018

AN-737: How ADIsimADC Models an ADC (Rev.B) 11/09/2007

AN-586: LVDS Outputs for High Speed A/D Converters (Rev.0) 02/14/2015

AN-741: Little Known Characteristics of Phase Noise (Rev.0) 11/29/2004

AN-501: Aperture Uncertainty and ADC System Performance (Rev.A) 02/14/2015

AN-345: Grounding for Low-and-High-Frequency Circuits 02/14/2015

AN-282: Fundamentals of Sampled Data Systems 02/14/2015

AN-935: Designing an ADC Transformer-Coupled Front End 09/01/2007

AN-1142: Techniques for High Speed ADC PCB Layout 01/12/2012

AN-835: Understanding High Speed ADC Testing and Evaluation 07/01/2020

AN-905: VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual 08/18/2020

AD6643/AD6649/AD9613/AD9643 Gerber Files 06/03/2011

AD6643/AD6649/AD9613/AD9643 Schematics 06/03/2011

AD6643 Quick Start Guide 06/03/2011

Design Resources 4

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.

Part Model	Pin/Package Drawing	Documentation	CAD Symbols, Footprints, and 3D Models
AD6643BCPZ-200	64-Lead LFCSP (9mm x 9mm w/ EP)	HTML Material Declaration HTML Reliablity Data	Ultra Librarian SamacSys
AD6643BCPZ-250	64-Lead LFCSP (9mm x 9mm w/ EP)	HTML Material Declaration HTML Reliablity Data	Ultra Librarian SamacSys
AD6643BCPZRL7-200	64-Lead LFCSP (9mm x 9mm w/ EP)	HTML Material Declaration HTML Reliablity Data	Ultra Librarian SamacSys
AD6643BCPZRL7-250	64-Lead LFCSP (9mm x 9mm w/ EP)	HTML Material Declaration HTML Reliablity Data	Ultra Librarian SamacSys

AD6643BCPZ-200
Pin/Package Drawing
64-Lead LFCSP (9mm x 9mm w/ EP)
Documentation

HTML Material Declaration

HTML Reliablity Data

CAD Symbols, Footprints, and 3D Models
Ultra Librarian
SamacSys

AD6643BCPZ-250
Pin/Package Drawing
64-Lead LFCSP (9mm x 9mm w/ EP)
Documentation

HTML Material Declaration

HTML Reliablity Data

CAD Symbols, Footprints, and 3D Models
Ultra Librarian
SamacSys

AD6643BCPZRL7-200
Pin/Package Drawing
64-Lead LFCSP (9mm x 9mm w/ EP)
Documentation

HTML Material Declaration

HTML Reliablity Data

CAD Symbols, Footprints, and 3D Models
Ultra Librarian
SamacSys

AD6643BCPZRL7-250
Pin/Package Drawing
64-Lead LFCSP (9mm x 9mm w/ EP)
Documentation

HTML Material Declaration

HTML Reliablity Data

CAD Symbols, Footprints, and 3D Models
Ultra Librarian
SamacSys

PCN/PDN Information

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Part Models

Product Lifecycle

PCN

Jun 26, 2023

- 23_0025

Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor

AD6643BCPZ-200

PRODUCTION

AD6643BCPZ-250

PRODUCTION

AD6643BCPZRL7-200

PRODUCTION

AD6643BCPZRL7-250

PRODUCTION

pdf

PCN23_0025_Form

xls

Material_Report

pdf

Package Outline Drawing

pdf

Qualification Results Summary

Jul 27, 2020

- 20_0126

Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea

AD6643BCPZ-200

PRODUCTION

AD6643BCPZ-250

PRODUCTION

AD6643BCPZRL7-200

PRODUCTION

AD6643BCPZRL7-250

PRODUCTION

pdf

PCN20_0126_Form

xls

Material_Report

pdf

Detailed Change Description

pdf

Package Outline Drawing

pdf

Qualification Plan

pdf

Qualification Results Summary

Filter by Model

Part Models

Product Lifecycle

PCN

Jun 26, 2023

- 23_0025

Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor

AD6643BCPZ-200

PRODUCTION

AD6643BCPZ-250

PRODUCTION

AD6643BCPZRL7-200

PRODUCTION

AD6643BCPZRL7-250

PRODUCTION

pdf

PCN23_0025_Form

xls

Material_Report

pdf

Package Outline Drawing

pdf

Qualification Results Summary

Jul 27, 2020

- 20_0126

Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea

AD6643BCPZ-200

PRODUCTION

AD6643BCPZ-250

PRODUCTION

AD6643BCPZRL7-200

PRODUCTION

AD6643BCPZRL7-250

PRODUCTION

pdf

PCN20_0126_Form

xls

Material_Report

pdf

Detailed Change Description

pdf

Package Outline Drawing

pdf

Qualification Plan

pdf

Qualification Results Summary

Companion Parts 14

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AD9514	RECOMMENDED FOR NEW DESIGNS	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9515	RECOMMENDED FOR NEW DESIGNS	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs
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AD9510	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
AD9511	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
AD9512	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs
AD9523	NOT RECOMMENDED FOR NEW DESIGNS	14-Output, Low Jitter Clock generator
AD9523-1	RECOMMENDED FOR NEW DESIGNS	Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs
AD9524	NOT RECOMMENDED FOR NEW DESIGNS	6 Output, Dual Loop Clock Generator
Digital Control VGAs2
ADL5202	Obsolete	Wide Dynamic Range, High Speed, Digitally Controlled VGA
AD8376	RECOMMENDED FOR NEW DESIGNS	Ultralow Distortion IF Dual VGA
Fully Differential Amplifiers1
ADL5562	RECOMMENDED FOR NEW DESIGNS	3.3 GHz Ultralow Distortion RF/IF Differential Amplifier
Single-Ended to Differential Amplifiers2
ADA4927-2	RECOMMENDED FOR NEW DESIGNS	Ultralow Distortion Current Feedback Differential ADC Driver
ADA4938-2	RECOMMENDED FOR NEW DESIGNS	Ultralow Distortion Differential ADC Driver (Dual)

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HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

Features and Benefits

64kB FIFO Depth
Works with single and multi-channel ADCs
Use with VisualAnalog^® software
Based on Virtex-4 FPGA
May require adaptor to interface with some ADC eval boards
Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
DDR Encode Rates on each channel

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Product Detail

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog^® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.

Resources

PDF

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2.1 M

Software

ZIP

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ZIP

Microsoft .NET Framework 3.5

ZIP

EVALC PC Board Gerber File

EVAL-AD6643

AD6643 Evaluation Board

AD9643-250EBZ Evaluation Board - Top View

AD9643-250EBZ Evaluation Board - Bottom View

AD6643 Evaluation Board

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EVAL-AD6643

AD6643 Evaluation Board

Features and Benefits

SPI interface for setup and control
External or AD9523 clocking option
Balun/transformer or amplifier input drive options
LDO regulator power supply
VisualAnalog and SPI controller software interfaces

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Product Detail

The AD6643-250EBZ is an evaluation board for the AD6643, dual 11-bit mixed-signal IF receiver ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations, It is designed to interface directly with the HSC-ADC-EVALCZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD6643.

The AD6643 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeed.converters@analog.com.

Resources

pdf

AD6643 Quick Start Guide

685 kB

pdf

UG-293: Evaluating the AD9643/AD9613/AD6649/AD6643 Analog-to-Digital Converters

2740 kB

zip

AD6643/AD6649/AD9613/AD9643 Gerber Files

480 kB

pdf

AD6643/AD6649/AD9613/AD9643 Schematics

99 kB

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

EVAL-AD6643

AD6643 Evaluation Board

Virtual Eval - BETA

Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.

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Visual Analog

For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.

Open Tool

ADIsimRF

ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.

Open Tool

S-Parameter 1

Simulation Model

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AD6643 LFCSP Analog Input S-Parameters

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9 Years Ago

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