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AD6649: IF Diversity Receiver Data Sheet (Rev. C)4/21/2011PDF1083 kB
Overview
Features and Benefits
- SNR = 73.0 dBFS in a 95 MHz BW at 185 MHz Ain and 245.76 MSPS
- SFDR = 85 dBc at 185 MHz Ain and 250 MSPS
- -151.2 dBFS/Hz Input Noise @ 220 MHz, -1dBFS Ain and 250MSPS
- 1.8 V analog and LVDS output supply operation
- Integer 1-to-8 input clock divider (625Mhz maximum input)
- Integrated dual-channel ADC
Sample rates up to 250 MSPS
IF sampling frequencies to 400 MHz
- Total Power consumption: 1W
- Integrated wideband digital downconverter (DDC)
32-bit complex, numerically controlled oscillator (NCO)
Sample Rate Converter and FIR filter with two modes
Real Output from an fs/4 output NCO - Fast detect bits for efficient AGC implementation
- Energy-saving power-down modes
- Decimated Interleaved ‘Real’ LVDS Data Outputs
- See datasheet for additional features
Product Details
The AD6649 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital downconverter (DDC) and a bypass-able sample rate converter (SRC). The AD6649 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO), an optional sample rate converter, a fixed FIR filter, and an fs/4 fixed-frequency NCO.
In addition to the receiver DDC, the AD6649 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.
After digital processing, data is routed directly to the 14-bit output port. These outputs operate at 1.8 V LVDS signal levels.
The AD6649 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. In diversity applications the output data format is real due to the final NCO which shifts the output center frequency to fs/4.
Flexible power-down options allow significant power savings, when desired.
Programming for setup and control is accomplished using a 3-pin SPI-compatible serial interface.
The AD6649 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
APPLICATIONS
- Communications
- Diversity radio systems
- Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE - General-purpose software radios
- Broadband data applications
PRODUCT HIGHLIGHTS
- Integrated dual, 14-bit, 250 MSPS ADC.
- Integrated wideband decimation filter and 32-bit complex NCO.
- Fast overrange and threshold detect.
- Proprietary differential input maintains excellent SNR performance for input frequencies up to 300 MHz.
- SYNC input allows synchronization of multiple devices.
- 3-pin, 1.8V SPI port for register programming and register readback.
Product Categories
Markets and Technologies
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (2)
Documentation & Resources
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AN-905: VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual8/18/2020
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AN-878: High Speed ADC SPI Control Software (Rev. A)3/20/2018PDF585 kB
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AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)5/12/2015PDF985 kB
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AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)2/14/2015PDF227 K
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AN-282: Fundamentals of Sampled Data Systems2/14/2015PDF2131 kB
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AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)2/14/2015PDF291K
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AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev. 0)2/14/2015PDF203 kB
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AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0)2/14/2015PDF363 kB
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AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. C)2/14/2015PDF427 K
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AN-345: Grounding for Low-and-High-Frequency Circuits2/14/2015PDF455 kB
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AN-586: LVDS Outputs for High Speed A/D Converters (Rev. 0)2/14/2015PDF207 kB
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AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0)2/2/2012PDF392 kB
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AN-737: How ADIsimADC Models an ADC (Rev. B)11/9/2007PDF373 kB
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AN-807: Multicarrier WCDMA Feasibility (Rev. 0)11/9/2007PDF969 kB
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AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)11/9/2007PDF1535 kB
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AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev. 0)7/26/2006PDF262 kB
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AN-741: Little Known Characteristics of Phase Noise (Rev. 0)11/29/2004PDF1679 kB
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UG-293: Evaluating the AD9643/AD9613/AD6649/AD6643 Analog-to-Digital Converters11/10/2011PDF2740 kB
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
S-Parameters
Design Tools
ADIsimRF
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
Visual Analog
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
Product Recommendations
AD6649 Companion Parts
Recommended Clock Drivers
- For low jitter performance: AD9510, AD9511, AD9512, AD9513, AD9514, AD9515.
- For low jitter performance along with on chip PLL and VCO: AD9523, AD9523-1, AD9524.
Recommended Driver Amplifiers
- For DC-coupled inputs: ADA4927-2, ADA4938-2.
- For differential RF/IF: ADL5562.
- For a fully differential input and output DVGA in digital communications systems: ADL5202, AD8376.
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
| Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
|---|---|---|---|---|
| AD6649BCPZ | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
| AD6649BCPZRL7 | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
| Wafer Fabrication Data |
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