AD6649

RECOMMENDED FOR NEW DESIGNS

AD6649

IF Diversity Receiver

RECOMMENDED FOR NEW DESIGNS

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Features

SNR = 73.0 dBFS in a 95 MHz BW at 185 MHz Ain and 245.76 MSPS
SFDR = 85 dBc at 185 MHz Ain and 250 MSPS
-151.2 dBFS/Hz Input Noise @ 220 MHz, -1dBFS Ain and 250MSPS
1.8 V analog and LVDS output supply operation
Integer 1-to-8 input clock divider (625Mhz maximum input)
Integrated dual-channel ADC
Sample rates up to 250 MSPS
IF sampling frequencies to 400 MHz

Total Power consumption: 1W
Integrated wideband digital downconverter (DDC)
32-bit complex, numerically controlled oscillator (NCO)
Sample Rate Converter and FIR filter with two modes
Real Output from an fs/4 output NCO
Fast detect bits for efficient AGC implementation
Energy-saving power-down modes
Decimated Interleaved ‘Real’ LVDS Data Outputs
See datasheet for additional features

Additional Details

The AD6649 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital downconverter (DDC) and a bypass-able sample rate converter (SRC). The AD6649 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO), an optional sample rate converter, a fixed FIR filter, and an fs/4 fixed-frequency NCO.

In addition to the receiver DDC, the AD6649 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.

After digital processing, data is routed directly to the 14-bit output port. These outputs operate at 1.8 V LVDS signal levels.

The AD6649 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. In diversity applications the output data format is real due to the final NCO which shifts the output center frequency to fs/4.

Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-pin SPI-compatible serial interface.

The AD6649 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

Applications

Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
General-purpose software radios
Broadband data applications

Product Highlights

Integrated dual, 14-bit, 250 MSPS ADC.
Integrated wideband decimation filter and 32-bit complex NCO.
Fast overrange and threshold detect.
Proprietary differential input maintains excellent SNR performance for input frequencies up to 300 MHz.
SYNC input allows synchronization of multiple devices.
3-pin, 1.8V SPI port for register programming and register readback.

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Ask a Question

Submit your question below and we will return the best answer from ADI’s knowledge database:

Other places you can find help

Support

Analog Devices Support Portal is a one-stop shop to answer all your ADI questions.

Visit the ADI Support Page

Ask the ADI community for help.

Ask the EngineerZone Community

FAQs

Sales & Ordering FAQs

Part Models 2

1ku List Price Starting From $98.04

Technical Documents 21

AD6649: IF Diversity Receiver Data Sheet (Rev.C) 04/21/2011

UG-293: Evaluating the AD9643/AD9613/AD6649/AD6643 Analog-to-Digital Converters 11/10/2011

AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev.0) 07/26/2006

AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev.0) 02/14/2015

AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev.0) 02/14/2015

AN-807: Multicarrier WCDMA Feasibility (Rev.0) 11/09/2007

AN-808: Multicarrier CDMA2000 Feasibility (Rev.0) 11/09/2007

AN-878: High Speed ADC SPI Control Software (Rev.A) 03/20/2018

AN-737: How ADIsimADC Models an ADC (Rev.B) 11/09/2007

AN-586: LVDS Outputs for High Speed A/D Converters (Rev.0) 02/14/2015

AN-741: Little Known Characteristics of Phase Noise (Rev.0) 11/29/2004

AN-501: Aperture Uncertainty and ADC System Performance (Rev.A) 02/14/2015

AN-345: Grounding for Low-and-High-Frequency Circuits 02/14/2015

AN-282: Fundamentals of Sampled Data Systems 02/14/2015

AN-935: Designing an ADC Transformer-Coupled Front End 09/01/2007

AN-1142: Techniques for High Speed ADC PCB Layout 01/12/2012

AN-905: VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual 08/18/2020

AN-835: Understanding High Speed ADC Testing and Evaluation 07/01/2020

AD6649 Quick Start Guide 06/03/2011

AD6643/AD6649/AD9613/AD9643 Gerber Files 06/03/2011

AD6643/AD6649/AD9613/AD9643 Schematics 06/03/2011

Design Resources 2

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.

Part Model	Pin/Package Drawing	Documentation	CAD Symbols, Footprints, and 3D Models
AD6649BCPZ	64-Lead LFCSP (9mm x 9mm w/ EP)	HTML Material Declaration HTML Reliablity Data	Ultra Librarian SamacSys
AD6649BCPZRL7	64-Lead LFCSP (9mm x 9mm w/ EP)	HTML Material Declaration HTML Reliablity Data	Ultra Librarian SamacSys

AD6649BCPZ
Pin/Package Drawing
64-Lead LFCSP (9mm x 9mm w/ EP)
Documentation

HTML Material Declaration

HTML Reliablity Data

CAD Symbols, Footprints, and 3D Models
Ultra Librarian
SamacSys

AD6649BCPZRL7
Pin/Package Drawing
64-Lead LFCSP (9mm x 9mm w/ EP)
Documentation

HTML Material Declaration

HTML Reliablity Data

CAD Symbols, Footprints, and 3D Models
Ultra Librarian
SamacSys

PCN/PDN Information

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Part Models

Product Lifecycle

PCN

Jun 26, 2023

- 23_0025

Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor

AD6649BCPZ

PRODUCTION

AD6649BCPZRL7

PRODUCTION

pdf

PCN23_0025_Form

xls

Material_Report

pdf

Package Outline Drawing

pdf

Qualification Results Summary

Jul 27, 2020

- 20_0126

Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea

AD6649BCPZ

PRODUCTION

AD6649BCPZRL7

PRODUCTION

pdf

PCN20_0126_Form

xls

Material_Report

pdf

Detailed Change Description

pdf

Package Outline Drawing

pdf

Qualification Plan

pdf

Qualification Results Summary

Filter by Model

Part Models

Product Lifecycle

PCN

Jun 26, 2023

- 23_0025

Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor

AD6649BCPZ

PRODUCTION

AD6649BCPZRL7

PRODUCTION

pdf

PCN23_0025_Form

xls

Material_Report

pdf

Package Outline Drawing

pdf

Qualification Results Summary

Jul 27, 2020

- 20_0126

Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea

AD6649BCPZ

PRODUCTION

AD6649BCPZRL7

PRODUCTION

pdf

PCN20_0126_Form

xls

Material_Report

pdf

Detailed Change Description

pdf

Package Outline Drawing

pdf

Qualification Plan

pdf

Qualification Results Summary

Companion Parts 14

Parts	Product Life Cycle	Description
Clock Distribution Devices3
AD9513	RECOMMENDED FOR NEW DESIGNS	800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9514	RECOMMENDED FOR NEW DESIGNS	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9515	RECOMMENDED FOR NEW DESIGNS	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs
Clock Generation Devices6
AD9510	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
AD9511	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
AD9512	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs
AD9523	NOT RECOMMENDED FOR NEW DESIGNS	14-Output, Low Jitter Clock generator
AD9523-1	RECOMMENDED FOR NEW DESIGNS	Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs
AD9524	NOT RECOMMENDED FOR NEW DESIGNS	6 Output, Dual Loop Clock Generator
Digital Control VGAs2
ADL5202	Obsolete	Wide Dynamic Range, High Speed, Digitally Controlled VGA
AD8376	RECOMMENDED FOR NEW DESIGNS	Ultralow Distortion IF Dual VGA
Fully Differential Amplifiers1
ADL5562	RECOMMENDED FOR NEW DESIGNS	3.3 GHz Ultralow Distortion RF/IF Differential Amplifier
Single-Ended to Differential Amplifiers2
ADA4927-2	RECOMMENDED FOR NEW DESIGNS	Ultralow Distortion Current Feedback Differential ADC Driver
ADA4938-2	RECOMMENDED FOR NEW DESIGNS	Ultralow Distortion Differential ADC Driver (Dual)

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EVAL-AD6649

AD6649 Evaluation Board

AD9643-250EBZ Evaluation Board - Top View

AD9643-250EBZ Evaluation Board - Bottom View

AD6649 Evaluation Board

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EVAL-AD6649

AD6649 Evaluation Board

Features and Benefits

Full featured evaluation board for the AD6649
SPI interface for setup and control
External or AD9523 clocking option
Balun/transformer or amplifier input drive options
LDO regulator power supply
VisualAnalog and SPI controller software interfaces

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Product Detail

The AD6649EBZ is an evaluation board for the AD6649, dual 14-bit mixed-signal IF receiver ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations, It is designed to interface directly with the HSC-ADC-EVALCZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD6649.

The AD6649 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeed.converters@analog.com.

Resources

zip

AD6643/AD6649/AD9613/AD9643 Gerber Files

480 kB

pdf

AD6643/AD6649/AD9613/AD9643 Schematics

99 kB

pdf

AD6649 Quick Start Guide

522 kB

pdf

UG-293: Evaluating the AD9643/AD9613/AD6649/AD6643 Analog-to-Digital Converters

2740 kB

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

Features and Benefits

64kB FIFO Depth
Works with single and multi-channel ADCs
Use with VisualAnalog^® software
Based on Virtex-4 FPGA
May require adaptor to interface with some ADC eval boards
Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
DDR Encode Rates on each channel

Buy Now View Details

Product Detail

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog^® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.

Resources

PDF

High Speed ADC USB FPGA Evaluation Kit, EVALC

2.1 M

Software

ZIP

High Speed ADC SPI Control Software

29.79 M

ZIP

Microsoft .NET Framework 3.5

ZIP

EVALC PC Board Gerber File

EVAL-AD6649

AD6649 Evaluation Board

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

Virtual Eval - BETA

Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.

Open Tool

IBIS Model 1

Simulation Model

IBIS Model

AD6649BCPZ (All Speed Grades)

Visual Analog

For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.

Open Tool

ADIsimRF

ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.

Open Tool

S-Parameter 1

Simulation Model

S-Parameter

AD6649 LFCSP Analog Input S-Parameter

575 kBB

1 Years Ago

RE: AD6649 restoring the IQ signal

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Data Sheet 1

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Evaluation Design File 3

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Tools & Simulations 5

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IBIS Model 1

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HSC-ADC-EVALCZ

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Virtual Eval - BETA

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